[U-Boot] [PATCH] da8xx: add support for multiple PLL controllers

nagabhushana.netagunte at ti.com
2011-07-28T16:25:38Z

From: Sudhakar Rajashekhara <sudhakar.raj@ti.com>

Add support for multiple PLL controllers and in the process,
modify the clk_get() to work for multiple PLL controllers.

Signed-off-by: Sudhakar Rajashekhara <sudhakar.raj@ti.com>
Signed-off-by: Nagabhushana Netagunte <nagabhushana.netagunte@ti.com>
---
arch/arm/cpu/arm926ejs/davinci/cpu.c | 27 +++++++++++++++----------
arch/arm/include/asm/arch-davinci/hardware.h | 1 +
2 files changed, 17 insertions(+), 11 deletions(-)

diff --git a/arch/arm/cpu/arm926ejs/davinci/cpu.c b/arch/arm/cpu/arm926ejs/davinci/cpu.c
index 8b57205..3ab56c7 100644
--- a/arch/arm/cpu/arm926ejs/davinci/cpu.c
+++ b/arch/arm/cpu/arm926ejs/davinci/cpu.c
@@ -37,6 +37,7 @@
#define PLLC_PLLDIV4 0x160
#define PLLC_PLLDIV5 0x164
#define PLLC_PLLDIV6 0x168
+#define PLLC_PLLDIV7 0x16c
#define PLLC_PLLDIV8 0x170
#define PLLC_PLLDIV9 0x174

@@ -61,11 +62,9 @@
#endif

#ifdef CONFIG_SOC_DA8XX
-const dv_reg * const sysdiv[7] = {
- &davinci_pllc_regs->plldiv1, &davinci_pllc_regs->plldiv2,
- &davinci_pllc_regs->plldiv3, &davinci_pllc_regs->plldiv4,
- &davinci_pllc_regs->plldiv5, &davinci_pllc_regs->plldiv6,
- &davinci_pllc_regs->plldiv7
+unsigned int sysdiv[9] = {
+ PLLC_PLLDIV1, PLLC_PLLDIV2, PLLC_PLLDIV3, PLLC_PLLDIV4, PLLC_PLLDIV5,
+ PLLC_PLLDIV6, PLLC_PLLDIV7, PLLC_PLLDIV8, PLLC_PLLDIV9
};

int clk_get(enum davinci_clk_ids id)
@@ -74,19 +73,26 @@ int clk_get(enum davinci_clk_ids id)
int pllm;
int post_div;
int pll_out;
+ volatile unsigned int pll_base;

pll_out = CONFIG_SYS_OSCIN_FREQ;

if (id == DAVINCI_AUXCLK_CLKID)
goto out;

+ if ((id >> 16) == 1)
+ pll_base = DAVINCI_PLL_CNTRL1_BASE;
+ else
+ pll_base = DAVINCI_PLL_CNTRL0_BASE;
+
+ id &= 0xFFFF;
+
/*
* Lets keep this simple. Combining operations can result in
* unexpected approximations
*/
- pre_div = (readl(&davinci_pllc_regs->prediv) &
- DAVINCI_PLLC_DIV_MASK) + 1;
- pllm = readl(&davinci_pllc_regs->pllm) + 1;
+ pre_div = (REG(pll_base + PLLC_PREDIV) & 0xff) + 1;
+ pllm = REG(pll_base + PLLC_PLLM) + 1;

pll_out /= pre_div;
pll_out *= pllm;
@@ -94,15 +100,14 @@ int clk_get(enum davinci_clk_ids id)
if (id == DAVINCI_PLLM_CLKID)
goto out;

- post_div = (readl(&davinci_pllc_regs->postdiv) &
- DAVINCI_PLLC_DIV_MASK) + 1;
+ post_div = (REG(pll_base + PLLC_POSTDIV) & 0xff) + 1;

pll_out /= post_div;

if (id == DAVINCI_PLLC_CLKID)
goto out;

- pll_out /= (readl(sysdiv[id - 1]) & DAVINCI_PLLC_DIV_MASK) + 1;
+ pll_out /= (REG(pll_base + sysdiv[id - 1]) & 0xff) + 1;

out:
return pll_out;
diff --git a/arch/arm/include/asm/arch-davinci/hardware.h b/arch/arm/include/asm/arch-davinci/hardware.h
index df3f549..d2b2989 100644
--- a/arch/arm/include/asm/arch-davinci/hardware.h
+++ b/arch/arm/include/asm/arch-davinci/hardware.h
@@ -129,6 +129,7 @@ typedef volatile unsigned int * dv_reg_p;
#define DAVINCI_TIMER1_BASE 0x01c21000
#define DAVINCI_WDOG_BASE 0x01c21000
#define DAVINCI_PLL_CNTRL0_BASE 0x01c11000
+#define DAVINCI_PLL_CNTRL1_BASE 0x01e1a000
#define DAVINCI_PSC0_BASE 0x01c10000
#define DAVINCI_PSC1_BASE 0x01e27000
#define DAVINCI_SPI0_BASE 0x01c41000
--
1.6.2.4