[U-Boot] [PATCH] socrates: Update NAND driver to new API.

[U-Boot] [PATCH] socrates: Update NAND driver to new API.

[Scott Wood]

Also, fix some minor formatting issues, and simplify the handling of
"state" for writes.

Signed-off-by: Scott Wood <scottwood@freescale.com>
---
I don't have hardware to test, so any help in that regard is appreciated.

Applied to u-boot-nand-flash.

 board/socrates/nand.c |   84 ++++++++++++++++++------------------------------
 1 files changed, 32 insertions(+), 52 deletions(-)

diff --git a/board/socrates/nand.c b/board/socrates/nand.c
index fc82ecb..6ec53f8 100644
--- a/board/socrates/nand.c
+++ b/board/socrates/nand.c
@@ -31,22 +31,20 @@
 static int state;
 static void nand_write_byte(struct mtd_info *mtd, u_char byte);
 static void nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len);
-static void nand_write_word(struct mtd_info *mtd, u16 word);
 static u_char nand_read_byte(struct mtd_info *mtd);
 static u16 nand_read_word(struct mtd_info *mtd);
 static void nand_read_buf(struct mtd_info *mtd, u_char *buf, int len);
 static int nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len);
 static int nand_device_ready(struct mtd_info *mtdinfo);
-static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd);
 
 #define FPGA_NAND_CMD_MASK		(0x7 << 28)
-#define FPGA_NAND_CMD_COMMAND	(0x0 << 28)
+#define FPGA_NAND_CMD_COMMAND		(0x0 << 28)
 #define FPGA_NAND_CMD_ADDR		(0x1 << 28)
 #define FPGA_NAND_CMD_READ		(0x2 << 28)
 #define FPGA_NAND_CMD_WRITE		(0x3 << 28)
 #define FPGA_NAND_BUSY			(0x1 << 15)
 #define FPGA_NAND_ENABLE		(0x1 << 31)
-#define FPGA_NAND_DATA_SHIFT	16
+#define FPGA_NAND_DATA_SHIFT		16
 
 /**
  * nand_write_byte -  write one byte to the chip
@@ -59,16 +57,6 @@ static void nand_write_byte(struct mtd_info *mtd, u_char byte)
 }
 
 /**
- * nand_write_word -  write one word to the chip
- * @mtd:	MTD device structure
- * @word:	data word to write
- */
-static void nand_write_word(struct mtd_info *mtd, u16 word)
-{
-	nand_write_buf(mtd, (const uchar *)&word, sizeof(word));
-}
-
-/**
  * nand_write_buf -  write buffer to chip
  * @mtd:	MTD device structure
  * @buf:	data buffer
@@ -78,18 +66,10 @@ static void nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
 {
 	int i;
 	struct nand_chip *this = mtd->priv;
-	long val;
-
-	if ((state & FPGA_NAND_CMD_MASK) == FPGA_NAND_CMD_MASK) {
-		/* Write data */
-		val = (state & FPGA_NAND_ENABLE) | FPGA_NAND_CMD_WRITE;
-	} else {
-		/* Write address or command */
-		val = state;
-	}
 
 	for (i = 0; i < len; i++) {
-		out_be32(this->IO_ADDR_W, val | (buf[i] << FPGA_NAND_DATA_SHIFT));
+		out_be32(this->IO_ADDR_W,
+			 state | (buf[i] << FPGA_NAND_DATA_SHIFT));
 	}
 }
 
@@ -148,7 +128,7 @@ static int nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
 
 	for (i = 0; i < len; i++) {
 		if (buf[i] != nand_read_byte(mtd));
-		return -EFAULT;
+			return -EFAULT;
 	}
 	return 0;
 }
@@ -171,42 +151,42 @@ static int nand_device_ready(struct mtd_info *mtdinfo)
  * @mtd:	MTD device structure
  * @cmd:	Command
  */
-static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd)
+static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl)
 {
+	if (ctrl & NAND_CTRL_CHANGE) {
+		state &= ~(FPGA_NAND_CMD_MASK | FPGA_NAND_ENABLE);
+
+		switch (ctrl & (NAND_ALE | NAND_CLE)) {
+		case 0:
+			state |= FPGA_NAND_CMD_WRITE;
+			break;
+
+		case NAND_ALE:
+			state |= FPGA_NAND_CMD_ADDR;
+			break;
 
-	switch(cmd) {
-	case NAND_CTL_CLRALE:
-		state |= FPGA_NAND_CMD_MASK; /* use all 1s to mark */
-		break;
-	case NAND_CTL_CLRCLE:
-		state |= FPGA_NAND_CMD_MASK; /* use all 1s to mark */
-		break;
-	case NAND_CTL_SETCLE:
-		state = (state & ~FPGA_NAND_CMD_MASK) | FPGA_NAND_CMD_COMMAND;
-		break;
-	case NAND_CTL_SETALE:
-		state = (state & ~FPGA_NAND_CMD_MASK) | FPGA_NAND_CMD_ADDR;
-		break;
-	case NAND_CTL_SETNCE:
-		state |= FPGA_NAND_ENABLE;
-		break;
-	case NAND_CTL_CLRNCE:
-		state &= ~FPGA_NAND_ENABLE;
-		break;
-	default:
-		printf("%s: unknown cmd %#x\n", __FUNCTION__, cmd);
-		break;
+		case NAND_CLE:
+			state |= FPGA_NAND_CMD_COMMAND;
+			break;
+
+		default:
+			printf("%s: unknown ctrl %#x\n", __FUNCTION__, ctrl);
+		}
+
+		if (ctrl & NAND_NCE)
+			state |= FPGA_NAND_ENABLE;
 	}
+
+	if (cmd != NAND_CMD_NONE)
+		nand_write_byte(mtdinfo, cmd);
 }
 
 int board_nand_init(struct nand_chip *nand)
 {
-	nand->hwcontrol = nand_hwcontrol;
-	nand->eccmode = NAND_ECC_SOFT;
+	nand->cmd_ctrl = nand_hwcontrol;
+	nand->ecc.mode = NAND_ECC_SOFT;
 	nand->dev_ready = nand_device_ready;
-	nand->write_byte = nand_write_byte;
 	nand->read_byte = nand_read_byte;
-	nand->write_word = nand_write_word;
 	nand->read_word = nand_read_word;
 	nand->write_buf = nand_write_buf;
 	nand->read_buf = nand_read_buf;
-- 
1.5.6.rc1.6.gc53ad

[U-Boot] [PATCH] socrates: Update NAND driver to new API.

[Detlev Zundel]

Hi Scott,

> Also, fix some minor formatting issues, and simplify the handling of
> "state" for writes.
>
> Signed-off-by: Scott Wood <scottwood@freescale.com>
> ---
> I don't have hardware to test, so any help in that regard is appreciated.

Testes on the actual hardware, works like a charm.

The patchseries that I just posted to update the socrates support works
on it flawlessly.

Thanks!
  Detlev

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