From: "Michael S. Tsirkin" <mst@redhat.com>
To: Gerd Hoffmann <kraxel@redhat.com>
Cc: "Dr. David Alan Gilbert" <dgilbert@redhat.com>,
Stefan Hajnoczi <stefanha@redhat.com>,
virtio-comment@lists.oasis-open.org
Subject: [virtio-comment] Re: PCI cap for larger offsets/lengths
Date: Tue, 27 Nov 2018 10:10:55 -0500 [thread overview]
Message-ID: <20181127100904-mutt-send-email-mst@kernel.org> (raw)
In-Reply-To: <20181126145145.cbuzccf3qo4z2nau@sirius.home.kraxel.org>
On Mon, Nov 26, 2018 at 03:51:45PM +0100, Gerd Hoffmann wrote:
> Hi,
>
> > > So, I'm wondering whenever it makes sense to just do the same for your
> > > device. Just use one pci bar as shared memory umbrella, specify that
> > > one using the virtio vendor cap, then have sub-regions within that bar
> > > for the various regions you have. Manage them dynamically (using
> > > device-specific virtio commands) or just have a static configuration (in
> > > device-specific config space).
> >
> > Ours are static subdivisions; so it felt easier to declare them; it's a
> > shame to make that device specific.
>
> Shared memory handling is device specific anyway, so I fail to see why
> this is a problem. Or do you want place virtio queues there (which
> could be common ground for multiple device types) ?
>
> > > That avoids the problem with multiple capabilities of the same kind, and
> > > it also avoids exhausting the cap IDs quicky if every device defines
> > > their own VIRTIO_FOO_DEVICE_PCI_SHMCAP_ID_BAR_REGION.
> >
> > Is having multiple capabilities of the same type actually a problem, or
> > is it just historical in the defitinition of virtio?
>
> I think the reason is that you can in theory have the same region twice,
> once in an IO bar and once in an MMIO bar, and then the guest could
> prefer the IO bar if possible and use the MMIO bar otherwise (PCIe slot
> without IO address window for example). I think that was never actually
> done in practice,
There's an option to enable that for AMD CPUs where MMIO
faults are slower than on intel CPUs.
> and for (prefetchable) memory bars it doesn't make
> sense at all. So that would unlikely be a problem in practice.
>
> Running out of capability IDs could become a real problem though.
>
> cheers,
> Gerd
We can always add more bits if we run out of these. there's
no real limit on capability size.
--
MST
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next prev parent reply other threads:[~2018-11-27 15:11 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20180921095459.GA2842@work-vm>
2018-11-26 11:16 ` [virtio-comment] Re: PCI cap for larger offsets/lengths Stefan Hajnoczi
[not found] ` <20181126135245.v4lklw6qwa2ggv4t@sirius.home.kraxel.org>
2018-11-26 14:03 ` Dr. David Alan Gilbert
[not found] ` <20181126145145.cbuzccf3qo4z2nau@sirius.home.kraxel.org>
2018-11-27 9:27 ` Stefan Hajnoczi
2018-11-27 15:10 ` Michael S. Tsirkin [this message]
2018-11-28 17:18 ` Dr. David Alan Gilbert
2018-11-28 20:16 ` Michael S. Tsirkin
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