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client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C From: Parav Pandit To: CC: , , Parav Pandit Date: Fri, 2 Jun 2023 01:03:00 +0300 Message-ID: <20230601220305.587034-3-parav@nvidia.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20230601220305.587034-1-parav@nvidia.com> References: <20230601220305.587034-1-parav@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT024:EE_|CO6PR12MB5443:EE_ X-MS-Office365-Filtering-Correlation-Id: 468412ed-13ab-4182-bf97-08db62ec07b3 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Ie5vzgXQvqZ2292rpdo04jRppb1qiQOnLj/vvdk5gilS/dAZk4mFbzVo6ARTB0aD2FzUJyg/OJlaUmJtvRUoiuVm479VaAun9WyRiDfpuOCNGshZWY6RlCm0oSNRnOEg2OCFqBdX4nYPhka63X9+5vX6XdRAQE/OkH9rGaA4uo3wSDQxRNxuXMYPr/NvWOIpAs3vfSh5/CdEnIqTdyqSNEycdtJ1smMsyXAC/MxSDBKEXzwlhtC2faPJf6LpzEYo6GsE1Tsvla5C+012/K5oErvo2F20ZXcXdywuuLTuXdsP/HwMpE3KDYH4T0ZtQ5Lwcx6lFNM/YFE7bFjntruZ39zphr7Q12S0JNNLBOpwNl5fnf4Cd9dRWx4NclevyvBd1vQJ1nyHzJ8EIniSqwFvHkv6gGc81Kh9XlftVT0fm6rIM5nejmDjQV0yf6MRCzFCHCDIiSNdxRZ8EevDyX8W/Ts8o6l8LgJ4IgqOV3+F/9/VGJh95/ED/0hS5bZs23sCdn3wyfmTpM5jAhoNFVyocCdsF2bLs5MwDfi5A5f8fVpbe81kZdOz35OwykBAUVbMp6mdxEuPyka4q1Bi6I8rDM4UYXYKm3kIWNaco9te3sH30UhUQZJ4OOsdrlhwUS89Q1uUJXyoKzbC9z408LD7mcDoyrse0Rgk7OeoPdmGH5xViB6uLdFqGJ+vQMP6TVVO1n129IllAnQHa6atrI806fpBJfM5UqQzz3vjs3I4tzKJ3w+2AooZf1TJerxs1MX4 X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230028)(4636009)(136003)(39860400002)(376002)(346002)(396003)(451199021)(46966006)(40470700004)(36840700001)(82310400005)(4326008)(7636003)(356005)(47076005)(107886003)(1076003)(26005)(40460700003)(86362001)(2906002)(5660300002)(8676002)(8936002)(186003)(6666004)(36756003)(2616005)(54906003)(426003)(336012)(316002)(82740400003)(41300700001)(40480700001)(16526019)(478600001)(6916009)(36860700001)(450100002)(70586007)(70206006);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Jun 2023 22:03:28.2050 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 468412ed-13ab-4182-bf97-08db62ec07b3 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT024.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CO6PR12MB5443 Subject: [virtio-comment] [PATCH requirements 2/7] net-features: Add low latency transmit queue requirements Add requirements for the low latency transmit queue. Signed-off-by: Parav Pandit --- net-workstream/features-1.4.md | 73 ++++++++++++++++++++++++++++++++++ 1 file changed, 73 insertions(+) diff --git a/net-workstream/features-1.4.md b/net-workstream/features-1.4.md index 03b4eb3..55f1b1f 100644 --- a/net-workstream/features-1.4.md +++ b/net-workstream/features-1.4.md @@ -7,6 +7,7 @@ together is desired while updating the virtio net interface. # 2. Summary 1. Device counters visible to the driver +2. Low latency tx virtqueue for PCI transport # 3. Requirements ## 3.1 Device counters @@ -34,3 +35,75 @@ together is desired while updating the virtio net interface. descriptors 2. le64 tx_gso_pkts: Packets send as host GSO sequence 3. le64 tx_pkts: Total packets send by the device + +## 3.2 Low PCI latency virtqueues +### 3.2.1 Low PCI latency tx virtqueue +1. Packet transmit descriptor should contain data descriptors count without any + indirection and without any O(N) search to find the end of a packet stream. + For example, a packet transmit descriptor (called vnet_tx_hdr_desc + subsequently) to contain a field num_next_desc for the packet stream + indicating that a packet is located N data descriptors. + +2. Packet transmit descriptor should contain segmentation offload-related fields + without any indirection. For example, packet transmit descriptor to contain + gso_type, gso_size/mss, header length, csum placement byte offset, and + csum start. + +3. Packet transmit descriptor should be able to place a small size packet that + does not have any L4 data after the vnet_tx_hdr_desc in the virtqueue memory. + For example a TCP ack only packet can fit in a descriptor memory which + otherwise consume more than 25% of metadata to describe the packet. + +4. Packet transmit descriptor should be able to place a full GSO header (L2 to + L4) after header descriptor and before data descriptors. For example, the + GSO header is placed after struct vnet_tx_hdr_desc in the virtqueue memory. + When such a GSO header is positioned adjacent to the packet transmit + descriptor, and when the GSO header is not aligned to 16B, the following + data descriptor to start on the 8B aligned boundary. + +5. An example of the above requirements at high level is: + +``` +struct vitio_packed_q_desc { + /* current desc for reference */ + u64 address; + u32 len; + u16 id; + u16 flags; +}; + +/* Constant size header descriptor for tx packets */ +struct vnet_tx_hdr_desc { + u16 flags; /* indicate how to parse next fields */ + u16 id; /* desc id to come back in completion */ + u8 num_next_desc; /* indicates the number of the next 16B data desc for this + * buffer. + */ + u8 gso_type; + le16 gso_hdr_len; + le16 gso_size; + le16 csum_start; + le16 csum_offset; + u8 inline_pkt_len; /* indicates the length of the inline packet after this + * desc + */ + u8 reserved; + u8 padding[]; +}; + +/* Example of a short packet or GSO header placed in the desc section of the vq + */ +struct vnet_tx_small_pkt_desc { + u8 raw_pkt[128]; +}; + +/* Example of header followed by data descriptor */ +struct vnet_tx_hdr_desc hdr_desc; +struct vnet_data_desc desc[2]; + +``` +6. Ability to zero pad the transmit completion when the transmit completion is + shorter than the CPU cache line size. + +7. Ability to place all transmit completion together with it per packet stream + transmit timestamp using single PCIe transcation. -- 2.26.2 This publicly archived list offers a means to provide input to the OASIS Virtual I/O Device (VIRTIO) TC. In order to verify user consent to the Feedback License terms and to minimize spam in the list archive, subscription is required before posting. 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