Discussion of the implementations of VIRTIO specification
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From: "Dr. David Alan Gilbert (git)" <dgilbert@redhat.com>
To: virtio-dev@lists.oasis-open.org,
	virtio-comment@lists.oasis-open.org, stefanha@redhat.com,
	cohuck@redhat.com
Cc: vgoyal@redhat.com
Subject: [virtio-comment] [PATCH v6 4/5] shared memory: Define PCI capability
Date: Wed, 10 Jul 2019 19:32:11 +0100	[thread overview]
Message-ID: <20190710183212.29420-5-dgilbert@redhat.com> (raw)
In-Reply-To: <20190710183212.29420-1-dgilbert@redhat.com>

From: "Dr. David Alan Gilbert" <dgilbert@redhat.com>

Define the PCI capability used for enumerating shared memory regions.

Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
---
 content.tex | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/content.tex b/content.tex
index d481359..1476b0e 100644
--- a/content.tex
+++ b/content.tex
@@ -689,6 +689,8 @@ \subsection{Virtio Structure PCI Capabilities}\label{sec:Virtio Transport Option
 #define VIRTIO_PCI_CAP_DEVICE_CFG        4
 /* PCI configuration access */
 #define VIRTIO_PCI_CAP_PCI_CFG           5
+/* Shared memory region */
+#define VIRTIO_PCI_CAP_SHARED_MEMORY_CFG 8
 \end{lstlisting}
 
         Any other value is reserved for future use.
@@ -1077,6 +1079,26 @@ \subsubsection{Device-specific configuration}\label{sec:Virtio Transport Options
 
 The \field{offset} for the device-specific configuration MUST be 4-byte aligned.
 
+\subsubsection{Shared memory capability}\label{sec:Virtio Transport Options / Virtio Over PCI Bus / PCI Device Layout / Shared memory capability}
+
+Shared memory regions \ref{sec:Basic Facilities of a Virtio
+Device / Shared Memory Regions} are enumerated on the PCI transport
+as a sequence of VIRTIO_PCI_CAP_SHARED_MEMORY_CFG capabilities, one per region.
+
+The capability is defined by a struct virtio_pci_cap64 and
+utilises the \field{cap.id} to allow multiple shared memory
+regions per device.
+The identifier in \field{cap.id} does not denote a certain order of
+preference; it is only used to uniquely identify a region.
+
+\devicenormative{\paragraph}{Device-specific configuration}{Virtio Transport Options / Virtio Over PCI Bus / PCI Device Layout / Shared memory capability}
+
+The region defined by the combination of the \field {cap.offset},
+\field {cap.offset_hi}, and \field {cap.length}, \field
+{cap.length_hi} fields MUST be contained within the declared bar.
+
+The \field{cap.id} MUST be unique for any one device instance.
+
 \subsubsection{PCI configuration access capability}\label{sec:Virtio Transport Options / Virtio Over PCI Bus / PCI Device Layout / PCI configuration access capability}
 
 The VIRTIO_PCI_CAP_PCI_CFG capability
-- 
2.21.0


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  parent reply	other threads:[~2019-07-10 18:32 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-07-10 18:32 [virtio-comment] [PATCH v6 0/5] Large shared memory regions Dr. David Alan Gilbert (git)
2019-07-10 18:32 ` [virtio-comment] [PATCH v6 1/5] shared memory: Define " Dr. David Alan Gilbert (git)
2019-07-10 18:32 ` [virtio-comment] [PATCH v6 2/5] pci: Define id field Dr. David Alan Gilbert (git)
2019-07-12  8:58   ` [virtio-comment] " Cornelia Huck
2019-07-10 18:32 ` [virtio-comment] [PATCH v6 3/5] pci: Define virtio_pci_cap64 Dr. David Alan Gilbert (git)
2019-07-10 18:32 ` Dr. David Alan Gilbert (git) [this message]
2019-07-12  9:01   ` [virtio-comment] Re: [PATCH v6 4/5] shared memory: Define PCI capability Cornelia Huck
2019-07-12 12:16     ` Dr. David Alan Gilbert
2019-07-10 18:32 ` [virtio-comment] [PATCH v6 5/5] shared memory: Define mmio registers Dr. David Alan Gilbert (git)

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