Discussion of the implementations of VIRTIO specification
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From: Parav Pandit <parav@nvidia.com>
To: mst@redhat.com, virtio-dev@lists.oasis-open.org, cohuck@redhat.com
Cc: virtio-comment@lists.oasis-open.org, shahafs@nvidia.com,
	Parav Pandit <parav@nvidia.com>
Subject: [PATCH v1 4/6] transport-pci: Correct spelling errors
Date: Fri, 17 Feb 2023 03:30:06 +0200	[thread overview]
Message-ID: <20230217013008.16062-5-parav@nvidia.com> (raw)
In-Reply-To: <20230217013008.16062-1-parav@nvidia.com>

Now that we have individual files, fix reported spelling errors.

While at it, remove trailing white spaces.

Signed-off-by: Parav Pandit <parav@nvidia.com>
---
changelog:
v0->v1:
- removed many trailing white spaces
---
 transport-pci.tex | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/transport-pci.tex b/transport-pci.tex
index 49c35bd..da1486a 100644
--- a/transport-pci.tex
+++ b/transport-pci.tex
@@ -5,7 +5,7 @@ \section{Virtio Over PCI Bus}\label{sec:Virtio Transport Options / Virtio Over P
 A Virtio device can be implemented as any kind of PCI device:
 a Conventional PCI device or a PCI Express
 device.  To assure designs meet the latest level
-requirements, see 
+requirements, see
 the PCI-SIG home page at \url{http://www.pcisig.com} for any
 approved changes.
 
@@ -14,7 +14,7 @@ \section{Virtio Over PCI Bus}\label{sec:Virtio Transport Options / Virtio Over P
 guest an interface that meets the specification requirements of
 the appropriate PCI specification: \hyperref[intro:PCI]{[PCI]}
 and \hyperref[intro:PCIe]{[PCIe]}
-respectively. 
+respectively.
 
 \subsection{PCI Device Discovery}\label{sec:Virtio Transport Options / Virtio Over PCI Bus / PCI Device Discovery}
 
@@ -586,7 +586,7 @@ \subsubsection{ISR status capability}\label{sec:Virtio Transport Options / Virti
 
 \devicenormative{\paragraph}{ISR status capability}{Virtio Transport Options / Virtio Over PCI Bus / PCI Device Layout / ISR status capability}
 
-The device MUST present at least one VIRTIO_PCI_CAP_ISR_CFG capability.  
+The device MUST present at least one VIRTIO_PCI_CAP_ISR_CFG capability.
 
 The device MUST set the Device Configuration Interrupt bit
 in \field{ISR status} before sending a device configuration
@@ -945,7 +945,7 @@ \subsubsection{Device Initialization}\label{sec:Virtio Transport Options / Virti
 \end{lstlisting}
 
 Note that mapping an event to vector might require device to
-allocate internal device resources, and thus could fail. 
+allocate internal device resources, and thus could fail.
 
 \devicenormative{\subparagraph}{MSI-X Vector Configuration}{Virtio Transport Options / Virtio Over PCI Bus / PCI-specific Initialization And Device Operation / Device Initialization / MSI-X Vector Configuration}
 
@@ -973,7 +973,7 @@ \subsubsection{Device Initialization}\label{sec:Virtio Transport Options / Virti
 unless it is impossible for the device to satisfy the mapping
 request.  Devices MUST report mapping
 failures by returning the NO_VECTOR value when the relevant
-\field{config_msix_vector}/\field{queue_msix_vector} field is read. 
+\field{config_msix_vector}/\field{queue_msix_vector} field is read.
 
 \drivernormative{\subparagraph}{MSI-X Vector Configuration}{Virtio Transport Options / Virtio Over PCI Bus / PCI-specific Initialization And Device Operation / Device Initialization / MSI-X Vector Configuration}
 
@@ -981,7 +981,7 @@ \subsubsection{Device Initialization}\label{sec:Virtio Transport Options / Virti
 Driver MAY fall back on using INT\#x interrupts for a device
 which only supports one MSI-X vector (MSI-X Table Size = 0).
 
-Driver MAY intepret the Table Size as a hint from the device
+Driver MAY interpret the Table Size as a hint from the device
 for the suggested number of MSI-X vectors to use.
 
 Driver MUST NOT attempt to map an event to a vector
-- 
2.26.2


  parent reply	other threads:[~2023-02-17  1:30 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-02-17  1:30 [PATCH v1 0/6] Split transport specific files Parav Pandit
2023-02-17  1:30 ` [PATCH v1 1/6] transport-pci: Split PCI transport to its own file Parav Pandit
2023-02-17  1:30 ` [PATCH v1 2/6] transport-mmio: Split MMIO " Parav Pandit
2023-02-17  1:30 ` [PATCH v1 3/6] transport-channelio: Split Channel IO " Parav Pandit
2023-02-17  1:30 ` Parav Pandit [this message]
2023-02-17  1:30 ` [PATCH v1 5/6] transport-mmio: Correct spelling errors Parav Pandit
2023-02-17 10:26   ` Michael S. Tsirkin
2023-02-17 15:59     ` Parav Pandit
2023-02-17  1:30 ` [PATCH v1 6/6] transport-channelio: " Parav Pandit
2023-02-17  9:14   ` Michael S. Tsirkin
2023-02-17 13:58     ` [virtio-comment] " Parav Pandit

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