From: Parav Pandit <parav@nvidia.com>
To: <mst@redhat.com>, <virtio-dev@lists.oasis-open.org>,
<cohuck@redhat.com>, <david.edmondson@oracle.com>
Cc: <sburla@marvell.com>, <jasowang@redhat.com>,
<virtio-comment@lists.oasis-open.org>, <shahafs@nvidia.com>,
Parav Pandit <parav@nvidia.com>
Subject: [virtio-dev] [PATCH v1 2/2] transport-pci: Add legacy register access conformance section
Date: Wed, 3 May 2023 06:26:59 +0300 [thread overview]
Message-ID: <20230503032659.530330-3-parav@nvidia.com> (raw)
In-Reply-To: <20230503032659.530330-1-parav@nvidia.com>
Add device and driver conformanace section for legacy registers access
commands interface.
Fixes: https://github.com/oasis-tcs/virtio-spec/issues/167
Signed-off-by: Parav Pandit <parav@nvidia.com>
---
conformance.tex | 2 ++
transport-pci-vf-regs.tex | 31 +++++++++++++++++++++++++++++++
2 files changed, 33 insertions(+)
diff --git a/conformance.tex b/conformance.tex
index 01ccd69..dbd8cd6 100644
--- a/conformance.tex
+++ b/conformance.tex
@@ -109,6 +109,7 @@ \section{Conformance Targets}\label{sec:Conformance / Conformance Targets}
\item \ref{drivernormative:Virtio Transport Options / Virtio Over PCI Bus / PCI Device Layout / PCI configuration access capability}
\item \ref{drivernormative:Virtio Transport Options / Virtio Over PCI Bus / PCI-specific Initialization And Device Operation / Device Initialization / MSI-X Vector Configuration}
\item \ref{drivernormative:Virtio Transport Options / Virtio Over PCI Bus / PCI-specific Initialization And Device Operation / Notification of Device Configuration Changes}
+\item \ref{drivernormative:Virtio Transport Options / Virtio Over PCI Bus / SR-IOV Legacy Registers Access}
\end{itemize}
\conformance{\subsection}{MMIO Driver Conformance}\label{sec:Conformance / Driver Conformance / MMIO Driver Conformance}
@@ -194,6 +195,7 @@ \section{Conformance Targets}\label{sec:Conformance / Conformance Targets}
\item \ref{devicenormative:Virtio Transport Options / Virtio Over PCI Bus / PCI-specific Initialization And Device Operation / Device Initialization / MSI-X Vector Configuration}
\item \ref{devicenormative:Virtio Transport Options / Virtio Over PCI Bus / PCI-specific Initialization And Device Operation / Used Buffer Notifications}
\item \ref{devicenormative:Virtio Transport Options / Virtio Over PCI Bus / PCI-specific Initialization And Device Operation / Notification of Device Configuration Changes}
+\item \ref{devicenormative:Virtio Transport Options / Virtio Over PCI Bus / SR-IOV Legacy Registers Access}
\end{itemize}
\conformance{\subsection}{MMIO Device Conformance}\label{sec:Conformance / Device Conformance / MMIO Device Conformance}
diff --git a/transport-pci-vf-regs.tex b/transport-pci-vf-regs.tex
index 16ced32..7d0574b 100644
--- a/transport-pci-vf-regs.tex
+++ b/transport-pci-vf-regs.tex
@@ -82,3 +82,34 @@ \subsubsection{Legacy Queue Notify Offset Query}\label{sec:Virtio Transport Opti
le64 offset; /* Byte offset within the BAR */
};
\end{lstlisting}
+
+\devicenormative{\paragraph}{SR-IOV VFs Legacy Registers Access}{Virtio Transport Options / Virtio Over PCI Bus / SR-IOV Legacy Registers Access}
+
+If the PCI PF device supports legacy registers access, it SHOULD set
+corresponding bits for commands VIRTIO_ADMIN_CMD_LREG_WRITE,
+VIRTIO_ADMIN_CMD_LREG_READ and VIRTIO_ADMIN_CMD_LQ_NOTIFY_QUERY in
+command result of VIRTIO_ADMIN_CMD_LIST_QUERY in
+\field{device_admin_cmd_opcodes}.
+
+The device MUST support legacy configuration registers to its defined width.
+
+The device MAY fail legacy configuration registers access when either the
+access is for an incorrct register width or if the register offset is incorrect.
+
+The device MUST allow access of one or multiple bytes of the registers when
+such register is defined as byte array, for example \field{mac} of \field{struct
+virtio_net_config} of the Network Device.
+
+\drivernormative{\paragraph}{SR-IOV VFs Legacy Registers Access}{Virtio Transport Options / Virtio Over PCI Bus / SR-IOV Legacy Registers Access}
+
+The driver MUST access legacy configuration registers to its defined width.
+
+The driver MUST access device specific registers to its defined width
+
+The driver MAY access one or multiple bytes of the device specific registers
+which are defined as byte array, for example \field{mac} of \field{struct
+virtio_net_config} of the Network Device.
+
+The driver SHOULD access all the bytes of a device specific registers in a
+single access when accessing a byte array, for example \field{mac} of
+\field{struct virtio_net_config} of the Network Device.
--
2.26.2
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next prev parent reply other threads:[~2023-05-03 3:27 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-03 3:26 [virtio-dev] [PATCH v1 0/2] transport-pci: Introduce legacy registers access using AQ Parav Pandit
2023-05-03 3:26 ` [virtio-dev] [PATCH v1 1/2] transport-pci: Introduce legacy registers access commands Parav Pandit
2023-05-03 5:42 ` [virtio-dev] " Michael S. Tsirkin
2023-05-03 14:47 ` Parav Pandit
2023-05-03 16:48 ` Michael S. Tsirkin
2023-05-03 17:21 ` Parav Pandit
2023-05-04 6:30 ` Michael S. Tsirkin
2023-05-03 5:50 ` Michael S. Tsirkin
2023-05-03 14:49 ` Parav Pandit
2023-05-03 16:49 ` Michael S. Tsirkin
2023-05-03 17:23 ` Parav Pandit
2023-05-04 6:30 ` Michael S. Tsirkin
2023-05-03 19:21 ` Michael S. Tsirkin
2023-05-03 19:38 ` Parav Pandit
2023-05-03 20:08 ` Michael S. Tsirkin
2023-05-03 20:13 ` Parav Pandit
2023-05-05 3:26 ` Jason Wang
2023-05-05 12:48 ` [virtio-dev] " Parav Pandit
2023-05-06 2:24 ` [virtio-dev] " Jason Wang
2023-05-06 2:25 ` Jason Wang
2023-05-03 3:26 ` Parav Pandit [this message]
2023-05-03 5:48 ` [virtio-dev] Re: [PATCH v1 2/2] transport-pci: Add legacy register access conformance section Michael S. Tsirkin
2023-05-03 14:53 ` [virtio-dev] Re: [virtio-comment] " Parav Pandit
2023-05-03 19:18 ` Michael S. Tsirkin
2023-05-03 19:56 ` [virtio-dev] " Parav Pandit
2023-05-03 10:16 ` [virtio-dev] Re: [PATCH v1 0/2] transport-pci: Introduce legacy registers access using AQ Michael S. Tsirkin
2023-05-03 14:57 ` Parav Pandit
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