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client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C From: Parav Pandit To: , , , CC: , , , , , , Parav Pandit Date: Sat, 6 May 2023 03:01:35 +0300 Message-ID: <20230506000135.628899-3-parav@nvidia.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20230506000135.628899-1-parav@nvidia.com> References: <20230506000135.628899-1-parav@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.126.231.37] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT008:EE_|LV3PR12MB9095:EE_ X-MS-Office365-Filtering-Correlation-Id: 886be52a-3e0a-4004-af69-08db4dc51ebd X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: dbMr7/Ezqvawwoh75vOh5kVAq5oyQWJOjQExfgE/XYT/zLvdQ1Rrr3mO6m/NEfpb8Y4z82Ti+mdXY1JQE/bMWGQwg5cn6rVrmKnO8I5G9JoqK/gHmuXD6c8JIWmA4z+E+esqju7n2DmYJX98CZvFvgW3aBYwozovzGbONZDGt7yF1hmaPWX7/KeP3WJAcFVJT9zTJEV3Cc4B7c/zyuulxOX5MGCRQ3Iw4Lc+0pfB7C3kYqEz1UY3CswJlMxyBFYvmkth0EecV5fZXlFFu1fbxBdsJ9XvGQr33FhQ8GclCImM6H4fcbnKYXk+agw6keCsNOkUsytJF0XzS48GCkJKG0vVrwIiaP/o59FXyIifefEA+t3xtYi3b78Fpc2XlNQ/vsFx131l/8r9rPDruONQg+mkqagIRXjbS8hhRl8NR1V3Rho5pFE5/AgGc6QL0A7YrsTjGwUj2loiOpV3NlJP4VQ9MLrJM19NMFw841tKLF8w43Wzyt8toOxkzF5gwrc6e0m3ceEvzjFImz4O/g8omw7YgVQx7PloiaV0Lua7h+7xcqGMCstpyMqGWeBmrHXkpbE20cqXCLENQtT2gUwWo+HdX7VfDcp+VULBP4PN+f6Ond4538vlw8b7CJTBFpKSO6xT5aKwTJiVhRl3L3V4Vl1XG3AiipGHY6QFcp14sWumLIShvAVsnun2LMz7Iy9xA5qQAce6BYDedKoJ8XfKvw== X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230028)(4636009)(39860400002)(376002)(396003)(136003)(346002)(451199021)(36840700001)(40470700004)(46966006)(40460700003)(83380400001)(2616005)(336012)(426003)(186003)(16526019)(36756003)(36860700001)(86362001)(82310400005)(356005)(82740400003)(40480700001)(7636003)(47076005)(8676002)(316002)(8936002)(2906002)(6666004)(41300700001)(5660300002)(478600001)(110136005)(54906003)(4326008)(70586007)(70206006)(1076003)(107886003)(26005);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 May 2023 00:02:02.0982 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 886be52a-3e0a-4004-af69-08db4dc51ebd X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT008.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV3PR12MB9095 Subject: [virtio-dev] [PATCH v2 2/2] transport-pci: Add legacy register access conformance section Add device and driver conformanace section for legacy registers access commands interface. Signed-off-by: Parav Pandit --- changelog: v1->v2: - addressed comments from Michael - removed duplicate and contradicting normatives to existing legacy interface section - added endianness normative for device specific region - updated conformance links --- conformance.tex | 2 ++ transport-pci-legacy-regs.tex | 27 +++++++++++++++++++++++++++ 2 files changed, 29 insertions(+) diff --git a/conformance.tex b/conformance.tex index 01ccd69..3f2d49e 100644 --- a/conformance.tex +++ b/conformance.tex @@ -109,6 +109,7 @@ \section{Conformance Targets}\label{sec:Conformance / Conformance Targets} \item \ref{drivernormative:Virtio Transport Options / Virtio Over PCI Bus / PCI Device Layout / PCI configuration access capability} \item \ref{drivernormative:Virtio Transport Options / Virtio Over PCI Bus / PCI-specific Initialization And Device Operation / Device Initialization / MSI-X Vector Configuration} \item \ref{drivernormative:Virtio Transport Options / Virtio Over PCI Bus / PCI-specific Initialization And Device Operation / Notification of Device Configuration Changes} +\item \ref{drivernormative:Virtio Transport Options / Virtio Over PCI Bus / Legacy Interfaces: SR-IOV VFs Registers Access} \end{itemize} \conformance{\subsection}{MMIO Driver Conformance}\label{sec:Conformance / Driver Conformance / MMIO Driver Conformance} @@ -194,6 +195,7 @@ \section{Conformance Targets}\label{sec:Conformance / Conformance Targets} \item \ref{devicenormative:Virtio Transport Options / Virtio Over PCI Bus / PCI-specific Initialization And Device Operation / Device Initialization / MSI-X Vector Configuration} \item \ref{devicenormative:Virtio Transport Options / Virtio Over PCI Bus / PCI-specific Initialization And Device Operation / Used Buffer Notifications} \item \ref{devicenormative:Virtio Transport Options / Virtio Over PCI Bus / PCI-specific Initialization And Device Operation / Notification of Device Configuration Changes} +\item \ref{devicenormative:Virtio Transport Options / Virtio Over PCI Bus / Legacy Interfaces: SR-IOV VFs Registers Access} \end{itemize} \conformance{\subsection}{MMIO Device Conformance}\label{sec:Conformance / Device Conformance / MMIO Device Conformance} diff --git a/transport-pci-legacy-regs.tex b/transport-pci-legacy-regs.tex index 9088fe6..4db578f 100644 --- a/transport-pci-legacy-regs.tex +++ b/transport-pci-legacy-regs.tex @@ -104,3 +104,30 @@ \subsubsection{Legacy Queue Notify Offset Query Command}\label{sec:Virtio Transp interface I/O space BAR and passthrough other PCI BARs and PCI device capabilities to the guest virtual machine without any translation. \end{note} + +\devicenormative{\paragraph}{SR-IOV VFs Legacy Registers Access}{Virtio Transport Options / Virtio Over PCI Bus / Legacy Interfaces: SR-IOV VFs Registers Access} + +If the PCI PF device supports legacy registers access for its group members, +the device MUST set all corresponding bits for commands VIRTIO_ADMIN_CMD_LREG_WRITE, +VIRTIO_ADMIN_CMD_LREG_READ and VIRTIO_ADMIN_CMD_LQ_NOTIFY_QUERY in +command result of VIRTIO_ADMIN_CMD_LIST_QUERY in +\field{device_admin_cmd_opcodes}. + +The device MUST encode and decode legacy device specific registers using +little-endian format. + +The device MUST fail VIRTIO_ADMIN_CMD_LREG_WRITE and VIRTIO_ADMIN_CMD_LREG_READ +commands for the invalid offset which is outside the legacy registers +address range. + +The PCI VF device SHOULD NOT use PCI BAR 0 when it prefers to support +legacy interface registers access. + +\drivernormative{\paragraph}{SR-IOV VFs Legacy Registers Access}{Virtio Transport Options / Virtio Over PCI Bus / Legacy Interfaces: SR-IOV VFs Registers Access} + +The driver MUST encode and decode legacy device specific registers using +little-endian format. + +The driver SHOULD send commands VIRTIO_ADMIN_CMD_LREG_WRITE and +VIRTIO_ADMIN_CMD_LREG_READ with a valid offset which is in the legacy +registers address range. -- 2.26.2 --------------------------------------------------------------------- To unsubscribe, e-mail: virtio-dev-unsubscribe@lists.oasis-open.org For additional commands, e-mail: virtio-dev-help@lists.oasis-open.org