[virtio-dev] [PATCH 08/11] transport-pci: Introduce virtio extended capability

Parav Pandit
2023-03-30T23:00:08Z

PCI device configuration space for capabilities is limited to only 192
bytes shared by many PCI capabilities of generic PCI device and virtio
specific.

Hence, introduce virtio extended capability that uses PCI Express
extended capability.
Subsequent patch uses this virtio extended capability.

Co-developed-by: Satananda Burla <sburla@marvell.com>
Signed-off-by: Parav Pandit <parav@nvidia.com>
---
transport-pci.tex | 69 ++++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 68 insertions(+), 1 deletion(-)

diff --git a/transport-pci.tex b/transport-pci.tex
index 665448e..aeda4a1 100644
--- a/transport-pci.tex
+++ b/transport-pci.tex
@@ -174,7 +174,8 @@ \subsection{Virtio Structure PCI Capabilities}\label{sec:Virtio Transport Option
the function, or accessed via the special VIRTIO_PCI_CAP_PCI_CFG field in the PCI configuration space.

The location of each structure is specified using a vendor-specific PCI capability located
-on the capability list in PCI configuration space of the device.
+on the capability list in PCI configuration space of the device
+unless stated otherwise.
This virtio structure capability uses little-endian format; all fields are
read-only for the driver unless stated otherwise:

@@ -301,6 +302,72 @@ \subsection{Virtio Structure PCI Capabilities}\label{sec:Virtio Transport Option
fields provide the most significant 32 bits of a total 64 bit offset and
length within the BAR specified by \field{cap.bar}.

+Virtio extended PCI Express capability structure defines
+the location of certain virtio device configuration related
+structures using PCI Express extended capability. Virtio
+extended PCI Express capability structure uses PCI Express
+vendor specific extended capability (VSEC). It has a below
+layout:
+
+\begin{lstlisting}
+struct pcie_ext_cap {
+ le16 cap_vendor_id; /* Generic PCI field: 0xB */
+ le16 cap_version : 2; /* Generic PCI field: 0 */
+ le16 next_cap_offset : 14; /* Generic PCI field: next cap or 0 */
+};
+
+struct virtio_pcie_ext_cap {
+ struct pcie_ext_cap pcie_ecap;
+ u8 cfg_type; /* Identifies the structure. */
+ u8 bar; /* Index of the BAR where its located */
+ u8 id; /* Multiple capabilities of the same type */
+ u8 zero_padding[1];
+ le64 offset; /* Offset with the bar */
+ le64 length; /* Length of the structure, in bytes. */
+ u8 data[]; /* Optional variable length data */
+};
+\end{lstlisting}
+
+This structure contains optional data, depending on
+\field{cfg_type}. The fields are interpreted as follows:
+
+\begin{description}
+\item[\field{cap_vendor_id}]
+ 0x0B; identifies a vendor-specific extended capability.
+
+\item[\field{cap_version}]
+ contains a value of 0.
+
+\item[\field{next_cap_offset}]
+ Offset to the next capability.
+
+\item[\field{cfg_type}]
+ follows the same definition as \field{cfg_type}
+ from the \field{struct virtio_pci_cap}.
+
+\item[\field{bar}]
+ follows the same same definition as \field{bar}
+ from the \field{struct virtio_pci_cap}.
+
+\item[\field{id}]
+ follows the same same definition as \field{id}
+ from the \field{struct virtio_pci_cap}.
+
+\item[\field{offset}]
+ indicates where the structure begins relative to the
+ base address associated with the BAR. The alignment
+ requirements of offset are indicated in each
+ structure-specific section that uses
+ \field{struct virtio_pcie_ext_cap}.
+
+\item[\field{length}]
+ indicates the length of the structure indicated by this
+ capability.
+
+\item[\field{data}]
+ optional data of this capability.
+\end{description}
+
\drivernormative{\subsubsection}{Virtio Structure PCI Capabilities}{Virtio Transport Options / Virtio Over PCI Bus / Virtio Structure PCI Capabilities}

The driver MUST ignore any vendor-specific capability structure which has
--
2.26.2