From: Parav Pandit <parav@nvidia.com>
To: "Michael S. Tsirkin" <mst@redhat.com>
Cc: virtio-dev@lists.oasis-open.org, cohuck@redhat.com,
david.edmondson@oracle.com, sburla@marvell.com,
jasowang@redhat.com, virtio-comment@lists.oasis-open.org,
shahafs@nvidia.com, Yishai Hadas <yishaih@nvidia.com>,
Maor Gottlieb <maorg@nvidia.com>
Subject: [virtio-dev] Re: [PATCH v1 0/2] transport-pci: Introduce legacy registers access using AQ
Date: Wed, 3 May 2023 10:57:39 -0400 [thread overview]
Message-ID: <5d2eb229-c07d-0476-60b3-cfc2f5316fb2@nvidia.com> (raw)
In-Reply-To: <20230503060538-mutt-send-email-mst@kernel.org>
On 5/3/2023 6:16 AM, Michael S. Tsirkin wrote:
> On Wed, May 03, 2023 at 06:26:57AM +0300, Parav Pandit wrote:
>> This patch introduces legacy registers access commands for the owner
>> group member PCI PF to access the legacy registers of the member VFs.
>>
>> If in future any SIOV devices to support legacy registers, they
>> can be easily supported using same commands by using the group
>> member identifiers of the future SIOV devices.
>
> Absolutely, but maybe we should not create work for this
> case by repeating PF/VF terminology everywhere?
>
If we omit the PF, VF it is kind of hard to explain things without any
tangible objects.
For example in your series lot of documentation of AQ is around SR-IOV
and VFs. If you take out that notion of VFs for inclusion of undefined
SIOV objects its hard as well.
So I think we can continue to talk about PF and VFs as is. When SIOV
enters, it will be easier to talk about it as VF or SIOV VDEV or
something similar.
>> More details as overview, motivation, use case are further described
>> below.
>>
>> Patch summary:
>> --------------
>> patch-1 adds administrative virtuqueue commands
>> patch-2 adds its conformance section
>>
>> This short series is on top of [1].
>> It uses the newly introduced administrative virtqueue facility with 3 new
>> opcodes and uses the existing virtio_admin_cmd.
>>
>> It is expected to go another rebase once v13 for [1] is rolled out and merged.
>>
>> [1] https://lore.kernel.org/virtio-comment/cover.1682354275.git.mst@redhat.com/T/#t
>>
>> Usecase:
>> --------
>> 1. A hypervisor/system needs to provide transitional
>> virtio devices to the guest VM at scale of thousands,
>> typically, one to eight devices per VM.
>>
>> 2. A hypervisor/system needs to provide such devices using a
>> vendor agnostic driver in the hypervisor system.
>>
>> 3. A hypervisor system prefers to have single stack regardless of
>> virtio device type (net/blk) and be future compatible with a
>> single vfio stack using SR-IOV or other scalable device
>> virtualization technology to map PCI devices to the guest VM.
>> (as transitional or otherwise)
>>
>> Motivation/Background:
>> ----------------------
>> The existing virtio transitional PCI device is missing support for
>> PCI SR-IOV based devices. Currently it does not work beyond
>> PCI PF, or as software emulated device in reality. Currently it
>> has below cited system level limitations:
>>
>> [a] PCIe spec citation:
>> VFs do not support I/O Space and thus VF BARs shall not indicate I/O Space.
>>
>> [b] cpu arch citiation:
>> Intel 64 and IA-32 Architectures Software Developer’s Manual:
>> The processor’s I/O address space is separate and distinct from
>> the physical-memory address space. The I/O address space consists
>> of 64K individually addressable 8-bit I/O ports, numbered 0 through FFFFH.
>>
>> [c] PCIe spec citation:
>> If a bridge implements an I/O address range,...I/O address range will be
>> aligned to a 4 KB boundary.
>>
>> Above usecase requirements can be solved by PCI PF group owner enabling
>> the access to its group member PCI VFs legacy registers using an admin
>> virtqueue of the group owner PCI PF.
>>
>> Software usage example:
>> -----------------------
>> The most common way to use and map to the guest VM is by
>> using vfio driver framework in Linux kernel.
>>
>> +----------------------+
>> |pci_dev_id = 0x100X |
>> +---------------|pci_rev_id = 0x0 |-----+
>> |vfio device |BAR0 = I/O region | |
>> | |Other attributes | |
>> | +----------------------+ |
>> | |
>> + +--------------+ +-----------------+ |
>> | |I/O BAR to AQ | | Other vfio | |
>> | |rd/wr mapper | | functionalities | |
>> | +--------------+ +-----------------+ |
>> | |
>> +------+-------------------------+-----------+
>> | |
>> +----+------------+ +----+------------+
>> | +-----+ | | PCI VF device A |
>> | | AQ |-------------+---->+-------------+ |
>> | +-----+ | | | | legacy regs | |
>> | PCI PF device | | | +-------------+ |
>> +-----------------+ | +-----------------+
>> |
>> | +----+------------+
>> | | PCI VF device N |
>> +---->+-------------+ |
>> | | legacy regs | |
>> | +-------------+ |
>> +-----------------+
>>
>> 2. Virtio pci driver to bind to the listed device id and
>> use it as native device in the host.
>>
>> 3. Use it in a light weight hypervisor to run bare-metal OS.
>>
>> Please review.
>>
>> Fixes: https://github.com/oasis-tcs/virtio-spec/issues/167
>> Signed-off-by: Parav Pandit <parav@nvidia.com>
>
> I don't see an overview here though.
>
I will add it in v2.
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prev parent reply other threads:[~2023-05-03 14:57 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-03 3:26 [virtio-dev] [PATCH v1 0/2] transport-pci: Introduce legacy registers access using AQ Parav Pandit
2023-05-03 3:26 ` [virtio-dev] [PATCH v1 1/2] transport-pci: Introduce legacy registers access commands Parav Pandit
2023-05-03 5:42 ` [virtio-dev] " Michael S. Tsirkin
2023-05-03 14:47 ` Parav Pandit
2023-05-03 16:48 ` Michael S. Tsirkin
2023-05-03 17:21 ` Parav Pandit
2023-05-04 6:30 ` Michael S. Tsirkin
2023-05-03 5:50 ` Michael S. Tsirkin
2023-05-03 14:49 ` Parav Pandit
2023-05-03 16:49 ` Michael S. Tsirkin
2023-05-03 17:23 ` Parav Pandit
2023-05-04 6:30 ` Michael S. Tsirkin
2023-05-03 19:21 ` Michael S. Tsirkin
2023-05-03 19:38 ` Parav Pandit
2023-05-03 20:08 ` Michael S. Tsirkin
2023-05-03 20:13 ` Parav Pandit
2023-05-05 3:26 ` Jason Wang
2023-05-05 12:48 ` [virtio-dev] " Parav Pandit
2023-05-06 2:24 ` [virtio-dev] " Jason Wang
2023-05-06 2:25 ` Jason Wang
2023-05-03 3:26 ` [virtio-dev] [PATCH v1 2/2] transport-pci: Add legacy register access conformance section Parav Pandit
2023-05-03 5:48 ` [virtio-dev] " Michael S. Tsirkin
2023-05-03 14:53 ` [virtio-dev] Re: [virtio-comment] " Parav Pandit
2023-05-03 19:18 ` Michael S. Tsirkin
2023-05-03 19:56 ` [virtio-dev] " Parav Pandit
2023-05-03 10:16 ` [virtio-dev] Re: [PATCH v1 0/2] transport-pci: Introduce legacy registers access using AQ Michael S. Tsirkin
2023-05-03 14:57 ` Parav Pandit [this message]
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