[virtio-dev] RE: [PATCH v2 0/2] transport-pci: Introduce legacy registers access using AQ

Parav Pandit
2023-05-15T15:31:45Z

> From: Jason Wang <jasowang@redhat.com>
> Sent: Monday, May 15, 2023 1:20 AM

>
> Right, but as discussed, a possible user is the SIOV transitional device via
> transport virtqueues.
>
>
> > transport vq might, but I am worried we'll have to spend extra
> > work clarifying it's a legacy interface. For example we will
> > have to explain that only 32 bits of features must be used.
> > Focusing more effort on transport vq is attractive though ...
> > It is worth examining this option in more depth.
> > Did you?
>
>
> My understanding is, for any case, we need such clarifications. What
> Parav proposed here is not the access to the actual registers but stick
> to the semantic of those registers. I think we must say high 32bits of
> the features must be assumed to be 0.
>
I am avoided duplicating anything that is already written for the PCI interface.
In legacy interface section of PCI, we already have:

"Note that only Feature Bits 0 to 31 are accessible through the Legacy Interface".
If MMIO is missing such line in existing interface, it is better to be added there.
It is not scope of this patch.