From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DF9531E0489; Wed, 30 Apr 2025 18:07:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.16 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746036469; cv=none; b=NOZYrxaFOvD6K0ascht7ry2z+G2gZZVogB5pVX49cacqEl4pVLGvFVbrSa3eqkOGK7DsxReMdhiPGGKyUQj8+h1UZGkU67XDBH9LQ/pt/+t85IeY+7Hp03VmKtUJGzEJ1V8FCqSRVVAQAgoSj5F4XdN4wTDM4fnSAXkB/owG2so= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746036469; c=relaxed/simple; bh=WI4EMFmcpg/gqdtcg3QiHPK9cuozRd9Cyp9RH7q5YJA=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=GkcO/umVqF/2DRBn/53cZX14Zlj0AlD43T+3+dPucI2XuK/4DizzaiBQALTyVheVBUHlNhxm22GhogGrRB43+2ZZLV6MHDeTESSKlNXZ7K+YzBHcZEzrSKiDo832ZfQ62L6lISwNQYsTJQd2bW8uXo9eBEH7TLE3/mf0lyHRWO4= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=gtYFc8Ap; arc=none smtp.client-ip=198.175.65.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="gtYFc8Ap" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1746036468; x=1777572468; h=message-id:date:mime-version:subject:to:cc:references: from:in-reply-to:content-transfer-encoding; bh=WI4EMFmcpg/gqdtcg3QiHPK9cuozRd9Cyp9RH7q5YJA=; b=gtYFc8Apm0+xdE3FYhJ3UM/p+VJSmlcAaOQFLOvab8wDi4+MPyjd7eDK kARUFXSGyQi+brWBkj5QLMBltj5mG4DRAdJlFsiFQWUeYI+w6u5XtfaRm rIqiSY5PDscIQ8RHDzxBqk0527QIYAzJ1jRdCEEzfLLnK70sk8bLglg7z AiwhfGey4loZV057I+tYE+xJBuaeHn9G3pFTdWMD7hhG+RbH0nEAUIzkL 2rUQgfF0OG5XTTZ6B9No4smpo8ZyrthwnDt9D1WckpHOucRCef7NI5SnL 1/2c8blPcnfx36g3Ltzc5CBli0rw6uqzaFSS1JETezOPQBJ+UI80myvCL w==; X-CSE-ConnectionGUID: LKEY2DHDQouzG8Kh+fSVLQ== X-CSE-MsgGUID: YlC610B1TVePGA8ZAGSYPw== X-IronPort-AV: E=McAfee;i="6700,10204,11419"; a="47798898" X-IronPort-AV: E=Sophos;i="6.15,252,1739865600"; d="scan'208";a="47798898" Received: from orviesa005.jf.intel.com ([10.64.159.145]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Apr 2025 11:07:46 -0700 X-CSE-ConnectionGUID: q7nmjbnpS6uUoCRFMVG4XQ== X-CSE-MsgGUID: BbI2PG4HSmqMtnjudrEanw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,252,1739865600"; d="scan'208";a="139369968" Received: from tfalcon-desk.amr.corp.intel.com (HELO [10.124.223.193]) ([10.124.223.193]) by orviesa005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Apr 2025 11:07:37 -0700 Message-ID: <019f6713-cfbd-466b-8fb5-dcd982cf8644@intel.com> Date: Wed, 30 Apr 2025 11:07:35 -0700 Precedence: bulk X-Mailing-List: virtualization@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 00/25] context_tracking,x86: Defer some IPIs until a user->kernel transition To: Steven Rostedt Cc: Valentin Schneider , linux-kernel@vger.kernel.org, virtualization@lists.linux.dev, linux-arm-kernel@lists.infradead.org, loongarch@lists.linux.dev, linux-riscv@lists.infradead.org, linux-perf-users@vger.kernel.org, kvm@vger.kernel.org, linux-arch@vger.kernel.org, linux-modules@vger.kernel.org, linux-trace-kernel@vger.kernel.org, rcu@vger.kernel.org, linux-hardening@vger.kernel.org, linux-kselftest@vger.kernel.org, bpf@vger.kernel.org, Juri Lelli , Marcelo Tosatti , Yair Podemsky , Josh Poimboeuf , Daniel Wagner , Petr Tesarik , Nicolas Saenz Julienne , Frederic Weisbecker , "Paul E. McKenney" , Dave Hansen , Sean Christopherson , Juergen Gross , Ajay Kaher , Alexey Makhalov , Broadcom internal kernel review list , Russell King , Catalin Marinas , Will Deacon , Huacai Chen , WANG Xuerui , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Thomas Gleixner , Ingo Molnar , Borislav Petkov , x86@kernel.org, "H. Peter Anvin" , Peter Zijlstra , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , "Liang, Kan" , Pawan Gupta , Paolo Bonzini , Arnd Bergmann , Jason Baron , Ard Biesheuvel , Luis Chamberlain , Petr Pavlu , Sami Tolvanen , Daniel Gomez , Naveen N Rao , Anil S Keshavamurthy , "David S. Miller" , Masami Hiramatsu , Neeraj Upadhyay , Joel Fernandes , Josh Triplett , Boqun Feng , Uladzislau Rezki , Mathieu Desnoyers , Lai Jiangshan , Zqiang , Vincent Guittot , Dietmar Eggemann , Ben Segall , Mel Gorman , Kees Cook , Shuah Khan , Masahiro Yamada , Alice Ryhl , Miguel Ojeda , "Mike Rapoport (Microsoft)" , Rong Xu , Rafael Aquini , Song Liu , Andrii Nakryiko , Dan Carpenter , Brian Gerst , "Kirill A. Shutemov" , Benjamin Berg , Vishal Annapurve , Randy Dunlap , John Stultz , Tiezhu Yang References: <20250429113242.998312-1-vschneid@redhat.com> <20250430132047.01d48647@gandalf.local.home> From: Dave Hansen Content-Language: en-US Autocrypt: addr=dave.hansen@intel.com; keydata= xsFNBE6HMP0BEADIMA3XYkQfF3dwHlj58Yjsc4E5y5G67cfbt8dvaUq2fx1lR0K9h1bOI6fC oAiUXvGAOxPDsB/P6UEOISPpLl5IuYsSwAeZGkdQ5g6m1xq7AlDJQZddhr/1DC/nMVa/2BoY 2UnKuZuSBu7lgOE193+7Uks3416N2hTkyKUSNkduyoZ9F5twiBhxPJwPtn/wnch6n5RsoXsb ygOEDxLEsSk/7eyFycjE+btUtAWZtx+HseyaGfqkZK0Z9bT1lsaHecmB203xShwCPT49Blxz VOab8668QpaEOdLGhtvrVYVK7x4skyT3nGWcgDCl5/Vp3TWA4K+IofwvXzX2ON/Mj7aQwf5W iC+3nWC7q0uxKwwsddJ0Nu+dpA/UORQWa1NiAftEoSpk5+nUUi0WE+5DRm0H+TXKBWMGNCFn c6+EKg5zQaa8KqymHcOrSXNPmzJuXvDQ8uj2J8XuzCZfK4uy1+YdIr0yyEMI7mdh4KX50LO1 pmowEqDh7dLShTOif/7UtQYrzYq9cPnjU2ZW4qd5Qz2joSGTG9eCXLz5PRe5SqHxv6ljk8mb ApNuY7bOXO/A7T2j5RwXIlcmssqIjBcxsRRoIbpCwWWGjkYjzYCjgsNFL6rt4OL11OUF37wL QcTl7fbCGv53KfKPdYD5hcbguLKi/aCccJK18ZwNjFhqr4MliQARAQABzUVEYXZpZCBDaHJp c3RvcGhlciBIYW5zZW4gKEludGVsIFdvcmsgQWRkcmVzcykgPGRhdmUuaGFuc2VuQGludGVs LmNvbT7CwXgEEwECACIFAlQ+9J0CGwMGCwkIBwMCBhUIAgkKCwQWAgMBAh4BAheAAAoJEGg1 lTBwyZKwLZUP/0dnbhDc229u2u6WtK1s1cSd9WsflGXGagkR6liJ4um3XCfYWDHvIdkHYC1t MNcVHFBwmQkawxsYvgO8kXT3SaFZe4ISfB4K4CL2qp4JO+nJdlFUbZI7cz/Td9z8nHjMcWYF IQuTsWOLs/LBMTs+ANumibtw6UkiGVD3dfHJAOPNApjVr+M0P/lVmTeP8w0uVcd2syiaU5jB aht9CYATn+ytFGWZnBEEQFnqcibIaOrmoBLu2b3fKJEd8Jp7NHDSIdrvrMjYynmc6sZKUqH2 I1qOevaa8jUg7wlLJAWGfIqnu85kkqrVOkbNbk4TPub7VOqA6qG5GCNEIv6ZY7HLYd/vAkVY E8Plzq/NwLAuOWxvGrOl7OPuwVeR4hBDfcrNb990MFPpjGgACzAZyjdmYoMu8j3/MAEW4P0z F5+EYJAOZ+z212y1pchNNauehORXgjrNKsZwxwKpPY9qb84E3O9KYpwfATsqOoQ6tTgr+1BR CCwP712H+E9U5HJ0iibN/CDZFVPL1bRerHziuwuQuvE0qWg0+0SChFe9oq0KAwEkVs6ZDMB2 P16MieEEQ6StQRlvy2YBv80L1TMl3T90Bo1UUn6ARXEpcbFE0/aORH/jEXcRteb+vuik5UGY 5TsyLYdPur3TXm7XDBdmmyQVJjnJKYK9AQxj95KlXLVO38lczsFNBFRjzmoBEACyAxbvUEhd GDGNg0JhDdezyTdN8C9BFsdxyTLnSH31NRiyp1QtuxvcqGZjb2trDVuCbIzRrgMZLVgo3upr MIOx1CXEgmn23Zhh0EpdVHM8IKx9Z7V0r+rrpRWFE8/wQZngKYVi49PGoZj50ZEifEJ5qn/H Nsp2+Y+bTUjDdgWMATg9DiFMyv8fvoqgNsNyrrZTnSgoLzdxr89FGHZCoSoAK8gfgFHuO54B lI8QOfPDG9WDPJ66HCodjTlBEr/Cwq6GruxS5i2Y33YVqxvFvDa1tUtl+iJ2SWKS9kCai2DR 3BwVONJEYSDQaven/EHMlY1q8Vln3lGPsS11vSUK3QcNJjmrgYxH5KsVsf6PNRj9mp8Z1kIG qjRx08+nnyStWC0gZH6NrYyS9rpqH3j+hA2WcI7De51L4Rv9pFwzp161mvtc6eC/GxaiUGuH BNAVP0PY0fqvIC68p3rLIAW3f97uv4ce2RSQ7LbsPsimOeCo/5vgS6YQsj83E+AipPr09Caj 0hloj+hFoqiticNpmsxdWKoOsV0PftcQvBCCYuhKbZV9s5hjt9qn8CE86A5g5KqDf83Fxqm/ vXKgHNFHE5zgXGZnrmaf6resQzbvJHO0Fb0CcIohzrpPaL3YepcLDoCCgElGMGQjdCcSQ+Ci FCRl0Bvyj1YZUql+ZkptgGjikQARAQABwsFfBBgBAgAJBQJUY85qAhsMAAoJEGg1lTBwyZKw l4IQAIKHs/9po4spZDFyfDjunimEhVHqlUt7ggR1Hsl/tkvTSze8pI1P6dGp2XW6AnH1iayn yRcoyT0ZJ+Zmm4xAH1zqKjWplzqdb/dO28qk0bPso8+1oPO8oDhLm1+tY+cOvufXkBTm+whm +AyNTjaCRt6aSMnA/QHVGSJ8grrTJCoACVNhnXg/R0g90g8iV8Q+IBZyDkG0tBThaDdw1B2l asInUTeb9EiVfL/Zjdg5VWiF9LL7iS+9hTeVdR09vThQ/DhVbCNxVk+DtyBHsjOKifrVsYep WpRGBIAu3bK8eXtyvrw1igWTNs2wazJ71+0z2jMzbclKAyRHKU9JdN6Hkkgr2nPb561yjcB8 sIq1pFXKyO+nKy6SZYxOvHxCcjk2fkw6UmPU6/j/nQlj2lfOAgNVKuDLothIxzi8pndB8Jju KktE5HJqUUMXePkAYIxEQ0mMc8Po7tuXdejgPMwgP7x65xtfEqI0RuzbUioFltsp1jUaRwQZ MTsCeQDdjpgHsj+P2ZDeEKCbma4m6Ez/YWs4+zDm1X8uZDkZcfQlD9NldbKDJEXLIjYWo1PH hYepSffIWPyvBMBTW2W5FRjJ4vLRrJSUoEfJuPQ3vW9Y73foyo/qFoURHO48AinGPZ7PC7TF vUaNOTjKedrqHkaOcqB185ahG2had0xnFsDPlx5y In-Reply-To: <20250430132047.01d48647@gandalf.local.home> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 4/30/25 10:20, Steven Rostedt wrote: > On Tue, 29 Apr 2025 09:11:57 -0700 > Dave Hansen wrote: > >> I don't think we should do this series. > > Could you provide more rationale for your decision. I talked about it a bit in here: > https://lore.kernel.org/all/408ebd8b-4bfb-4c4f-b118-7fe853c6e897@intel.com/ But, basically, this series puts a new onus on the entry code: it can't touch the vmalloc() area ... except the LDT ... and except the PEBS buffers. If anyone touches vmalloc()'d memory (or anything else that eventually gets deferred), they crash. They _only_ crash on these NOHZ_FULL systems. Putting new restrictions on the entry code is really nasty. Let's say a new hardware feature showed up that touched vmalloc()'d memory in the entry code. Probably, nobody would notice until they got that new hardware and tried to do a NOHZ_FULL workload. It might take years to uncover, once that hardware was out in the wild. I have a substantial number of gray hairs from dealing with corner cases in the entry code. You _could_ make it more debuggable. Could you make this work for all tasks, not just NOHZ_FULL? The same logic _should_ apply. It would be inefficient, but would provide good debugging coverage. I also mentioned this earlier, but PTI could be leveraged here to ensure that the TLB is flushed properly. You could have the rule that anything mapped into the user page table can't have a deferred flush and then do deferred flushes at SWITCH_TO_KERNEL_CR3 time. Yeah, that's in arch-specific assembly, but it's a million times easier to reason about because the window where a deferred-flush allocation might bite you is so small. Look at the syscall code for instance: > SYM_CODE_START(entry_SYSCALL_64) > swapgs > movq %rsp, PER_CPU_VAR(cpu_tss_rw + TSS_sp2) > SWITCH_TO_KERNEL_CR3 scratch_reg=%rsp You can _trivially_ audit this and know that swapgs doesn't touch memory and that as long as PER_CPU_VAR()s and the process stack don't have their mappings munged and flushes deferred that this would be correct. >> If folks want this functionality, they should get a new CPU that can >> flush the TLB without IPIs. > > That's a pretty heavy handed response. I'm not sure that's always a > feasible solution. > > From my experience in the world, software has always been around to fix the > hardware, not the other way around ;-) Both AMD and Intel have hardware to do it. ARM CPUs do it too, I think. You can go buy the Intel hardware off the shelf today.