[PATCH 3/4] Pte xchg optimization.patch

[PATCH 3/4] Pte xchg optimization.patch

[Zachary Amsden]

In situations where page table updates need only be made locally, and there
is no cross-processor A/D bit races involved, we need not use the heavyweight
xchg instruction to atomically fetch and clear page table entries.  Instead,
we can just read and clear them directly.

This introduces a neat optimization for non-SMP kernels; drop the atomic
xchg operations from page table updates.

Thanks to Michel Lespinasse for noting this potential optimization.

Signed-off-by: Zachary Amsden <zach@vmware.com>

diff -r 47495b2532b3 include/asm-i386/pgtable-2level.h
--- a/include/asm-i386/pgtable-2level.h	Wed Apr 11 18:23:01 2007 -0700
+++ b/include/asm-i386/pgtable-2level.h	Wed Apr 11 18:23:39 2007 -0700
@@ -41,10 +41,24 @@ static inline void native_pte_clear(stru
 	*xp = __pte(0);
 }
 
+/* local pte updates need not use xchg for locking */
+static inline pte_t native_local_ptep_get_and_clear(pte_t *ptep)
+{
+	pte_t res;
+
+	res = *ptep;
+	native_pte_clear(NULL, 0, ptep);
+	return res;
+}
+
+#ifdef CONFIG_SMP
 static inline pte_t native_ptep_get_and_clear(pte_t *xp)
 {
 	return __pte(xchg(&xp->pte_low, 0));
 }
+#else
+#define native_ptep_get_and_clear(xp) native_local_ptep_get_and_clear(xp)
+#endif
 
 #define pte_page(x)		pfn_to_page(pte_pfn(x))
 #define pte_none(x)		(!(x).pte_low)
diff -r 47495b2532b3 include/asm-i386/pgtable-3level.h
--- a/include/asm-i386/pgtable-3level.h	Wed Apr 11 18:23:01 2007 -0700
+++ b/include/asm-i386/pgtable-3level.h	Wed Apr 11 18:23:05 2007 -0700
@@ -139,6 +139,17 @@ static inline void pud_clear (pud_t * pu
 #define pmd_offset(pud, address) ((pmd_t *) pud_page(*(pud)) + \
 			pmd_index(address))
 
+/* local pte updates need not use xchg for locking */
+static inline pte_t native_local_ptep_get_and_clear(pte_t *ptep)
+{
+	pte_t res;
+	
+	res = *ptep;
+	native_pte_clear(NULL, 0, ptep);
+	return res;
+}
+
+#ifdef CONFIG_SMP
 static inline pte_t native_ptep_get_and_clear(pte_t *ptep)
 {
 	pte_t res;
@@ -150,6 +161,9 @@ static inline pte_t native_ptep_get_and_
 
 	return res;
 }
+#else
+#define native_ptep_get_and_clear(xp) native_local_ptep_get_and_clear(xp)
+#endif
 
 #define __HAVE_ARCH_PTE_SAME
 static inline int pte_same(pte_t a, pte_t b)

Re: [PATCH 3/4] Pte xchg optimization.patch

[Dave Jones]

On Wed, Apr 11, 2007 at 10:30:58PM -0700, Zachary Amsden wrote:
 > In situations where page table updates need only be made locally, and there
 > is no cross-processor A/D bit races involved, we need not use the heavyweight
 > xchg instruction to atomically fetch and clear page table entries.  Instead,
 > we can just read and clear them directly.
 > 
 > This introduces a neat optimization for non-SMP kernels; drop the atomic
 > xchg operations from page table updates.

Would it be feasible to do this using the smp_alternatives stuff?
Given many distros are now shipping SMP-only kernels, it'd be nice
to get that win without using having to rebuild their kernels.

	Dave

-- 
http://www.codemonkey.org.uk

Re: [PATCH 3/4] Pte xchg optimization.patch

[Zachary Amsden]

Dave Jones wrote:
> On Wed, Apr 11, 2007 at 10:30:58PM -0700, Zachary Amsden wrote:
>  > In situations where page table updates need only be made locally, and there
>  > is no cross-processor A/D bit races involved, we need not use the heavyweight
>  > xchg instruction to atomically fetch and clear page table entries.  Instead,
>  > we can just read and clear them directly.
>  > 
>  > This introduces a neat optimization for non-SMP kernels; drop the atomic
>  > xchg operations from page table updates.
>
> Would it be feasible to do this using the smp_alternatives stuff?
> Given many distros are now shipping SMP-only kernels, it'd be nice
> to get that win without using having to rebuild their kernels.
>   

That's a good point. It is a fairly straightforward substitution for the 
static case:

xchg reg, mem

to

mov mem, reg
mov imm, mem

I'll give it a spin and see how it drives. It is, though, less obvious 
how easy it will be for PAE kernels.

Zach