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[31.30.173.16]) by smtp.gmail.com with ESMTPSA id a88-20020a509ee1000000b0056dc0e21a7dsm6860407edf.4.2024.04.04.04.55.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Apr 2024 04:55:39 -0700 (PDT) Date: Thu, 4 Apr 2024 13:55:38 +0200 From: Andrew Jones To: Atish Patra Cc: linux-kernel@vger.kernel.org, Ajay Kaher , Alexandre Ghiti , Alexey Makhalov , Anup Patel , Conor Dooley , Juergen Gross , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Paolo Bonzini , Paul Walmsley , Shuah Khan , virtualization@lists.linux.dev, VMware PV-Drivers Reviewers , Will Deacon , x86@kernel.org Subject: Re: [PATCH v5 07/22] drivers/perf: riscv: Fix counter mask iteration for RV32 Message-ID: <20240404-f10f72395cc0b25971541ece@orel> References: <20240403080452.1007601-1-atishp@rivosinc.com> <20240403080452.1007601-8-atishp@rivosinc.com> Precedence: bulk X-Mailing-List: virtualization@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240403080452.1007601-8-atishp@rivosinc.com> On Wed, Apr 03, 2024 at 01:04:36AM -0700, Atish Patra wrote: > For RV32, used_hw_ctrs can have more than 1 word if the firmware chooses > to interleave firmware/hardware counters indicies. Even though it's a > unlikely scenario, handle that case by iterating over all the words > instead of just using the first word. > > Signed-off-by: Atish Patra > --- > drivers/perf/riscv_pmu_sbi.c | 21 ++++++++++++--------- > 1 file changed, 12 insertions(+), 9 deletions(-) > > diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c > index 8c3475d55433..82336fec82b8 100644 > --- a/drivers/perf/riscv_pmu_sbi.c > +++ b/drivers/perf/riscv_pmu_sbi.c > @@ -771,13 +771,15 @@ static inline void pmu_sbi_stop_hw_ctrs(struct riscv_pmu *pmu) > { > struct cpu_hw_events *cpu_hw_evt = this_cpu_ptr(pmu->hw_events); > unsigned long flag = 0; > + int i; > > if (sbi_pmu_snapshot_available()) > flag = SBI_PMU_STOP_FLAG_TAKE_SNAPSHOT; > > - /* No need to check the error here as we can't do anything about the error */ > - sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_STOP, 0, > - cpu_hw_evt->used_hw_ctrs[0], flag, 0, 0, 0); > + for (i = 0; i < BITS_TO_LONGS(RISCV_MAX_COUNTERS); i++) > + /* No need to check the error here as we can't do anything about the error */ > + sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_STOP, i * BITS_PER_LONG, > + cpu_hw_evt->used_hw_ctrs[i], flag, 0, 0, 0); > } > > /* > @@ -789,7 +791,7 @@ static inline void pmu_sbi_stop_hw_ctrs(struct riscv_pmu *pmu) > static noinline void pmu_sbi_start_ovf_ctrs_sbi(struct cpu_hw_events *cpu_hw_evt, > unsigned long ctr_ovf_mask) > { > - int idx = 0; > + int idx = 0, i; > struct perf_event *event; > unsigned long flag = SBI_PMU_START_FLAG_SET_INIT_VALUE; > unsigned long ctr_start_mask = 0; > @@ -797,11 +799,12 @@ static noinline void pmu_sbi_start_ovf_ctrs_sbi(struct cpu_hw_events *cpu_hw_evt > struct hw_perf_event *hwc; > u64 init_val = 0; > > - ctr_start_mask = cpu_hw_evt->used_hw_ctrs[0] & ~ctr_ovf_mask; > - > - /* Start all the counters that did not overflow in a single shot */ > - sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, 0, ctr_start_mask, > - 0, 0, 0, 0); > + for (i = 0; i < BITS_TO_LONGS(RISCV_MAX_COUNTERS); i++) { > + ctr_start_mask = cpu_hw_evt->used_hw_ctrs[i] & ~ctr_ovf_mask; > + /* Start all the counters that did not overflow in a single shot */ > + sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, i * BITS_PER_LONG, ctr_start_mask, > + 0, 0, 0, 0); > + } > > /* Reinitialize and start all the counter that overflowed */ > while (ctr_ovf_mask) { > -- > 2.34.1 > Reviewed-by: Andrew Jones