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[2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id jy5-20020a170907762500b00a466af74ef2sm806704ejc.2.2024.04.05.05.50.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Apr 2024 05:50:32 -0700 (PDT) Date: Fri, 5 Apr 2024 14:50:31 +0200 From: Andrew Jones To: Atish Patra Cc: linux-kernel@vger.kernel.org, Anup Patel , Ajay Kaher , Alexandre Ghiti , Alexey Makhalov , Conor Dooley , Juergen Gross , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Paolo Bonzini , Paul Walmsley , Shuah Khan , virtualization@lists.linux.dev, VMware PV-Drivers Reviewers , Will Deacon , x86@kernel.org Subject: Re: [PATCH v5 20/22] KVM: riscv: selftests: Add SBI PMU selftest Message-ID: <20240405-d1a4cb9a441a05a9d2f8b1c8@orel> References: <20240403080452.1007601-1-atishp@rivosinc.com> <20240403080452.1007601-21-atishp@rivosinc.com> Precedence: bulk X-Mailing-List: virtualization@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240403080452.1007601-21-atishp@rivosinc.com> On Wed, Apr 03, 2024 at 01:04:49AM -0700, Atish Patra wrote: ... > +static void test_pmu_basic_sanity(void) > +{ > + long out_val = 0; > + bool probe; > + struct sbiret ret; > + int num_counters = 0, i; > + union sbi_pmu_ctr_info ctrinfo; > + > + probe = guest_sbi_probe_extension(SBI_EXT_PMU, &out_val); > + GUEST_ASSERT(probe && out_val == 1); > + > + num_counters = get_num_counters(); > + > + for (i = 0; i < num_counters; i++) { > + ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_GET_INFO, i, > + 0, 0, 0, 0, 0); > + > + /* There can be gaps in logical counter indicies*/ > + if (ret.error) > + continue; > + GUEST_ASSERT_NE(ret.value, 0); > + > + ctrinfo.value = ret.value; > + > + /** > + * Accesibillity check of hardware and read capability of firmware counters. Accessibility > + * The spec doesn't mandate any initial value. No need to check any value. > + */ > + read_counter(i, ctrinfo); > + } > + > + GUEST_DONE(); > +} > + > +static void run_vcpu(struct kvm_vcpu *vcpu) > +{ > + struct ucall uc; > + > + vcpu_run(vcpu); > + switch (get_ucall(vcpu, &uc)) { > + case UCALL_ABORT: > + REPORT_GUEST_ASSERT(uc); > + break; > + case UCALL_DONE: > + case UCALL_SYNC: > + break; > + default: > + TEST_FAIL("Unknown ucall %lu", uc.cmd); > + break; > + } > +} > + > +void test_vm_destroy(struct kvm_vm *vm) > +{ > + memset(ctrinfo_arr, 0, sizeof(union sbi_pmu_ctr_info) * RISCV_MAX_PMU_COUNTERS); > + counter_mask_available = 0; > + kvm_vm_free(vm); > +} > + > +static void test_vm_basic_test(void *guest_code) > +{ > + struct kvm_vm *vm; > + struct kvm_vcpu *vcpu; > + > + vm = vm_create_with_one_vcpu(&vcpu, guest_code); > + __TEST_REQUIRE(__vcpu_has_sbi_ext(vcpu, KVM_RISCV_SBI_EXT_PMU), > + "SBI PMU not available, skipping test"); > + vm_init_vector_tables(vm); > + /* Illegal instruction handler is required to verify read access without configuration */ > + vm_install_exception_handler(vm, EXC_INST_ILLEGAL, guest_illegal_exception_handler); I still don't see where the "verify" part is. The handler doesn't record that it had to handle anything. > + > + vcpu_init_vector_tables(vcpu); > + run_vcpu(vcpu); > + > + test_vm_destroy(vm); > +} > + > +static void test_vm_events_test(void *guest_code) > +{ > + struct kvm_vm *vm = NULL; > + struct kvm_vcpu *vcpu = NULL; > + > + vm = vm_create_with_one_vcpu(&vcpu, guest_code); > + __TEST_REQUIRE(__vcpu_has_sbi_ext(vcpu, KVM_RISCV_SBI_EXT_PMU), > + "SBI PMU not available, skipping test"); > + run_vcpu(vcpu); > + > + test_vm_destroy(vm); > +} > + > +int main(void) > +{ > + test_vm_basic_test(test_pmu_basic_sanity); > + pr_info("SBI PMU basic test : PASS\n"); > + > + test_vm_events_test(test_pmu_events); > + pr_info("SBI PMU event verification test : PASS\n"); > + > + return 0; > +} > -- > 2.34.1 > Thanks, drew