From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pj1-f74.google.com (mail-pj1-f74.google.com [209.85.216.74]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3D16F1A8F71 for ; Thu, 27 Feb 2025 02:19:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.74 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740622747; cv=none; b=ZoSgr5W1s/hm1MtH1KG8RZwpwbgAcioEa32yYxQSfPQbDDbpRGzw8wnSWLg16J3W/63wXcSpp8IEnC8fAsKEnJ3/zWWIiUAFLwcSLQ0gplfiws1k19D7iJgzCAYaoINt+9YYqpwiFZ8HTGZFxrbb1+g+8Klfjtaf96yPkXsnXRg= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740622747; c=relaxed/simple; bh=vr3NG+3TNhQXw/Ld9LNbvZ/lm9g+GH2tsC78kbtC4nE=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=JETEbbpqqzYZFkmz28bf37lZbngLNhE6qkIr5fmwOsPnyfSLd/pMcgcZXUpAddPTmY1saFbm1nVa4t9vQJRuI4rLxnnfmqJLsnxjjU0g/VHTcG7lLUMnT+4tygywGjcGY9GqiXvvY+OuBEPFKcR373UnoOdlub/9LESNW8jq1ns= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=Gj5oHZBh; arc=none smtp.client-ip=209.85.216.74 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="Gj5oHZBh" Received: by mail-pj1-f74.google.com with SMTP id 98e67ed59e1d1-2fc1cb0c2cbso1525411a91.1 for ; Wed, 26 Feb 2025 18:19:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1740622744; x=1741227544; darn=lists.linux.dev; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:from:to:cc:subject:date:message-id:reply-to; bh=KtBuHiug8RyBl7zdSfnpeCyQMsoAneIAJhrbW8v3FfQ=; b=Gj5oHZBhUnHE278yTeVUMH9cx4eA5f5bY76L6DltIALEAJpdgw7ahgJjQiXHbti7gg ZDz99ue0uranMNkHrYn5lOQadayycU+I75vGKD5o0djWial0N3WSjp8+xaGcYvJpjQ9r Jrug5VlwytI0bS6mRoTFRY9ljGru0qBLa93SJmsxDDZbOtLYTdQLJ03AeWJQeR6T9uOj 8as0Am9h6pBlPmNb9tJ4EGQQrupFF03I6/EG2ZtNBQaUK2nB0ygItloiIlsFFG996Ese 6pjeyFKtuAVVP+U5UaHwNrP9/vSqkCPBxyu22NLocwSu0bvnumAZHPFPWQ4VoFbVWVvM EQzA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1740622744; x=1741227544; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=KtBuHiug8RyBl7zdSfnpeCyQMsoAneIAJhrbW8v3FfQ=; b=oxVkDZxmBQdWPfZE98U5mj518iP/andHPnzbGrHXRMkGaDRI/E8PIwhKUip9MP88tG LZak1mZ6Uf9L/pSTmJX2OT2lozbZvdHHV4iu0FDSP+dSVQUFBBqf0DPCfSS+Tilp+fET AJkC2J0w31IGOi63LE4VCrsCaWVUgsbq8vlS4njuE0l1llnGKC4fv+VWnU8t8YWfM0Qm +iHefBI510zLkaonVE6VrOD1MnTG/s3HwpnFmQ+T97sHRlntsCveiznEj4UFfsnXsSEC pVnHk5LAf1rNBXEaUvB9v668xeRNRmTcD55iHuQjnGlHlP0VracmB7t5u7JO+8ZK5vbB dRbA== X-Forwarded-Encrypted: i=1; AJvYcCWO4HQ514/tUUH8U45X9DJNLXIUH7I3yoqdquc2/yCobbHkk6QGQ1kBwIYD8/qfzcftj/G80Yv0ww60L21riw==@lists.linux.dev X-Gm-Message-State: AOJu0YwOIFnncs/dtqCq412JHFqF77FRAkSLunzukHkjAj0uHC2BZJ3V /Kc+7mDb9nuI0fQAOBigf1Am7vlSpjDeoeMvdZ8/fk5jZ2T+T914MIfbXjVx7qxNEs4uwgGWGe7 TdA== X-Google-Smtp-Source: AGHT+IEZuLrSoCpVWZXJcy9TmAp9qIs68IJxs5ZGUPBqjbzVn9jX2mg4vMG9kljqKgFFkZhvGqcDyGJTu1M= X-Received: from pjbsn14.prod.google.com ([2002:a17:90b:2e8e:b0:2fc:15bf:92f6]) (user=seanjc job=prod-delivery.src-stubby-dispatcher) by 2002:a17:90b:1f8e:b0:2ee:b8ac:73b0 with SMTP id 98e67ed59e1d1-2fe68acd43fmr15933009a91.2.1740622744544; Wed, 26 Feb 2025 18:19:04 -0800 (PST) Reply-To: Sean Christopherson Date: Wed, 26 Feb 2025 18:18:17 -0800 In-Reply-To: <20250227021855.3257188-1-seanjc@google.com> Precedence: bulk X-Mailing-List: virtualization@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250227021855.3257188-1-seanjc@google.com> X-Mailer: git-send-email 2.48.1.711.g2feabab25a-goog Message-ID: <20250227021855.3257188-2-seanjc@google.com> Subject: [PATCH v2 01/38] x86/tsc: Add a standalone helpers for getting TSC info from CPUID.0x15 From: Sean Christopherson To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "Kirill A. Shutemov" , Paolo Bonzini , Sean Christopherson , Juergen Gross , "K. Y. Srinivasan" , Haiyang Zhang , Wei Liu , Dexuan Cui , Ajay Kaher , Jan Kiszka , Andy Lutomirski , Peter Zijlstra , Daniel Lezcano , John Stultz Cc: linux-kernel@vger.kernel.org, linux-coco@lists.linux.dev, kvm@vger.kernel.org, virtualization@lists.linux.dev, linux-hyperv@vger.kernel.org, xen-devel@lists.xenproject.org, Tom Lendacky , Nikunj A Dadhania Content-Type: text/plain; charset="UTF-8" Extract retrieval of TSC frequency information from CPUID into standalone helpers so that TDX guest support and kvmlock can reuse the logic. Provide a version that includes the multiplier math as TDX in particular does NOT want to use native_calibrate_tsc()'s fallback logic that derives the TSC frequency based on CPUID.0x16 when the core crystal frequency isn't known. Opportunsitically drop native_calibrate_tsc()'s "== 0" and "!= 0" check in favor of the kernel's preferred style. No functional change intended. Signed-off-by: Sean Christopherson --- arch/x86/include/asm/tsc.h | 9 +++++ arch/x86/kernel/tsc.c | 67 +++++++++++++++++++++++++------------- 2 files changed, 53 insertions(+), 23 deletions(-) diff --git a/arch/x86/include/asm/tsc.h b/arch/x86/include/asm/tsc.h index 94408a784c8e..a4d84f721775 100644 --- a/arch/x86/include/asm/tsc.h +++ b/arch/x86/include/asm/tsc.h @@ -28,6 +28,15 @@ static inline cycles_t get_cycles(void) } #define get_cycles get_cycles +struct cpuid_tsc_info { + unsigned int denominator; + unsigned int numerator; + unsigned int crystal_khz; + unsigned int tsc_khz; +}; +extern int cpuid_get_tsc_info(struct cpuid_tsc_info *info); +extern int cpuid_get_tsc_freq(struct cpuid_tsc_info *info); + extern void tsc_early_init(void); extern void tsc_init(void); extern void mark_tsc_unstable(char *reason); diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c index 34dec0b72ea8..93713eb81f52 100644 --- a/arch/x86/kernel/tsc.c +++ b/arch/x86/kernel/tsc.c @@ -655,46 +655,67 @@ static unsigned long quick_pit_calibrate(void) return delta; } +int cpuid_get_tsc_info(struct cpuid_tsc_info *info) +{ + unsigned int ecx_hz, edx; + + memset(info, 0, sizeof(*info)); + + if (boot_cpu_data.cpuid_level < CPUID_LEAF_TSC) + return -ENOENT; + + /* CPUID 15H TSC/Crystal ratio, plus optionally Crystal Hz */ + cpuid(CPUID_LEAF_TSC, &info->denominator, &info->numerator, &ecx_hz, &edx); + + if (!info->denominator || !info->numerator) + return -ENOENT; + + /* + * Note, some CPUs provide the multiplier information, but not the core + * crystal frequency. The multiplier information is still useful for + * such CPUs, as the crystal frequency can be gleaned from CPUID.0x16. + */ + info->crystal_khz = ecx_hz / 1000; + return 0; +} + +int cpuid_get_tsc_freq(struct cpuid_tsc_info *info) +{ + if (cpuid_get_tsc_info(info) || !info->crystal_khz) + return -ENOENT; + + info->tsc_khz = info->crystal_khz * info->numerator / info->denominator; + return 0; +} + /** * native_calibrate_tsc - determine TSC frequency * Determine TSC frequency via CPUID, else return 0. */ unsigned long native_calibrate_tsc(void) { - unsigned int eax_denominator, ebx_numerator, ecx_hz, edx; - unsigned int crystal_khz; + struct cpuid_tsc_info info; if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) return 0; - if (boot_cpu_data.cpuid_level < CPUID_LEAF_TSC) + if (cpuid_get_tsc_info(&info)) return 0; - eax_denominator = ebx_numerator = ecx_hz = edx = 0; - - /* CPUID 15H TSC/Crystal ratio, plus optionally Crystal Hz */ - cpuid(CPUID_LEAF_TSC, &eax_denominator, &ebx_numerator, &ecx_hz, &edx); - - if (ebx_numerator == 0 || eax_denominator == 0) - return 0; - - crystal_khz = ecx_hz / 1000; - /* * Denverton SoCs don't report crystal clock, and also don't support * CPUID_LEAF_FREQ for the calculation below, so hardcode the 25MHz * crystal clock. */ - if (crystal_khz == 0 && - boot_cpu_data.x86_vfm == INTEL_ATOM_GOLDMONT_D) - crystal_khz = 25000; + if (!info.crystal_khz && boot_cpu_data.x86_vfm == INTEL_ATOM_GOLDMONT_D) + info.crystal_khz = 25000; /* * TSC frequency reported directly by CPUID is a "hardware reported" * frequency and is the most accurate one so far we have. This * is considered a known frequency. */ - if (crystal_khz != 0) + if (info.crystal_khz) setup_force_cpu_cap(X86_FEATURE_TSC_KNOWN_FREQ); /* @@ -702,15 +723,15 @@ unsigned long native_calibrate_tsc(void) * clock, but we can easily calculate it to a high degree of accuracy * by considering the crystal ratio and the CPU speed. */ - if (crystal_khz == 0 && boot_cpu_data.cpuid_level >= CPUID_LEAF_FREQ) { + if (!info.crystal_khz && boot_cpu_data.cpuid_level >= CPUID_LEAF_FREQ) { unsigned int eax_base_mhz, ebx, ecx, edx; cpuid(CPUID_LEAF_FREQ, &eax_base_mhz, &ebx, &ecx, &edx); - crystal_khz = eax_base_mhz * 1000 * - eax_denominator / ebx_numerator; + info.crystal_khz = eax_base_mhz * 1000 * + info.denominator / info.numerator; } - if (crystal_khz == 0) + if (!info.crystal_khz) return 0; /* @@ -727,10 +748,10 @@ unsigned long native_calibrate_tsc(void) * lapic_timer_period here to avoid having to calibrate the APIC * timer later. */ - lapic_timer_period = crystal_khz * 1000 / HZ; + lapic_timer_period = info.crystal_khz * 1000 / HZ; #endif - return crystal_khz * ebx_numerator / eax_denominator; + return info.crystal_khz * info.numerator / info.denominator; } static unsigned long cpu_khz_from_cpuid(void) -- 2.48.1.711.g2feabab25a-goog