From: "Xin Li (Intel)" <xin@zytor.com>
To: linux-kernel@vger.kernel.org, kvm@vger.kernel.org,
linux-perf-users@vger.kernel.org, linux-hyperv@vger.kernel.org,
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Subject: [PATCH v4 06/15] x86/xen/msr: Return u64 consistently in Xen PMC read functions
Date: Sun, 27 Apr 2025 02:20:18 -0700 [thread overview]
Message-ID: <20250427092027.1598740-7-xin@zytor.com> (raw)
In-Reply-To: <20250427092027.1598740-1-xin@zytor.com>
The pv_ops PMC read API is defined as:
u64 (*read_pmc)(int counter);
But Xen PMC read functions return unsigned long long, make them
return u64 consistently.
Signed-off-by: Xin Li (Intel) <xin@zytor.com>
Reviewed-by: Juergen Gross <jgross@suse.com>
Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org>
---
arch/x86/xen/pmu.c | 6 +++---
arch/x86/xen/xen-ops.h | 2 +-
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/x86/xen/pmu.c b/arch/x86/xen/pmu.c
index f06987b0efc3..9c1682af620a 100644
--- a/arch/x86/xen/pmu.c
+++ b/arch/x86/xen/pmu.c
@@ -346,7 +346,7 @@ bool pmu_msr_write(unsigned int msr, uint32_t low, uint32_t high, int *err)
return true;
}
-static unsigned long long xen_amd_read_pmc(int counter)
+static u64 xen_amd_read_pmc(int counter)
{
struct xen_pmu_amd_ctxt *ctxt;
uint64_t *counter_regs;
@@ -366,7 +366,7 @@ static unsigned long long xen_amd_read_pmc(int counter)
return counter_regs[counter];
}
-static unsigned long long xen_intel_read_pmc(int counter)
+static u64 xen_intel_read_pmc(int counter)
{
struct xen_pmu_intel_ctxt *ctxt;
uint64_t *fixed_counters;
@@ -396,7 +396,7 @@ static unsigned long long xen_intel_read_pmc(int counter)
return arch_cntr_pair[counter].counter;
}
-unsigned long long xen_read_pmc(int counter)
+u64 xen_read_pmc(int counter)
{
if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
return xen_amd_read_pmc(counter);
diff --git a/arch/x86/xen/xen-ops.h b/arch/x86/xen/xen-ops.h
index 63c13a2ccf55..735f58780704 100644
--- a/arch/x86/xen/xen-ops.h
+++ b/arch/x86/xen/xen-ops.h
@@ -277,7 +277,7 @@ static inline void xen_pmu_finish(int cpu) {}
bool pmu_msr_read(unsigned int msr, uint64_t *val, int *err);
bool pmu_msr_write(unsigned int msr, uint32_t low, uint32_t high, int *err);
int pmu_apic_update(uint32_t reg);
-unsigned long long xen_read_pmc(int counter);
+u64 xen_read_pmc(int counter);
#ifdef CONFIG_SMP
--
2.49.0
next prev parent reply other threads:[~2025-04-27 9:21 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-04-27 9:20 [PATCH v4 00/15] MSR code cleanup part one Xin Li (Intel)
2025-04-27 9:20 ` [PATCH v4 01/15] x86/msr: Add missing includes of <asm/msr.h> Xin Li (Intel)
2025-04-29 9:45 ` Ilpo Järvinen
2025-04-29 17:27 ` Xin Li
2025-04-30 4:20 ` Michael Kelley
2025-04-30 9:12 ` Xin Li
2025-04-30 8:41 ` Xin Li
2025-04-30 9:17 ` Ilpo Järvinen
2025-04-30 17:34 ` Xin Li
2025-05-01 5:42 ` [PATCH v4A " Xin Li (Intel)
2025-05-02 13:13 ` Ilpo Järvinen
2025-05-02 17:50 ` Xin Li
2025-04-27 9:20 ` [PATCH v4 02/15] x86/msr: Move rdtsc{,_ordered}() to <asm/tsc.h> Xin Li (Intel)
2025-05-02 8:02 ` Ingo Molnar
2025-05-02 18:09 ` Xin Li
2025-05-02 8:18 ` Ingo Molnar
2025-05-02 18:01 ` Xin Li
2025-05-02 8:52 ` Ingo Molnar
2025-05-02 18:00 ` Xin Li
2025-04-27 9:20 ` [PATCH v4 03/15] x86/msr: Remove rdpmc() Xin Li (Intel)
2025-04-27 9:20 ` [PATCH v4 04/15] x86/msr: Rename rdpmcl() to rdpmc() Xin Li (Intel)
2025-04-27 9:20 ` [PATCH v4 05/15] x86/msr: Convert the rdpmc() macro into an always inline function Xin Li (Intel)
2025-04-27 9:20 ` Xin Li (Intel) [this message]
2025-04-27 9:20 ` [PATCH v4 07/15] x86/msr: Convert __wrmsr() uses to native_wrmsr{,q}() uses Xin Li (Intel)
2025-04-27 9:20 ` [PATCH v4 08/15] x86/msr: Add the native_rdmsrq() helper Xin Li (Intel)
2025-04-27 9:20 ` [PATCH v4 09/15] x86/msr: Convert __rdmsr() uses to native_rdmsrq() uses Xin Li (Intel)
2025-04-27 9:20 ` [PATCH v4 10/15] x86/xen/msr: Remove calling native_{read,write}_msr{,_safe}() in pmu_msr_{read,write}() Xin Li (Intel)
2025-05-02 8:30 ` Ingo Molnar
2025-04-27 9:20 ` [PATCH v4 11/15] x86/xen/msr: Remove pmu_msr_{read,write}() Xin Li (Intel)
2025-04-27 9:20 ` [PATCH v4 12/15] x86/xen/msr: Remove the error pointer argument from set_seg() Xin Li (Intel)
2025-04-27 9:20 ` [PATCH v4 13/15] x86/pvops/msr: refactor pv_cpu_ops.write_msr{,_safe}() Xin Li (Intel)
2025-04-27 9:20 ` [PATCH v4 14/15] x86/msr: Replace wrmsr(msr, low, 0) with wrmsrq(msr, low) Xin Li (Intel)
2025-04-27 9:20 ` [PATCH v4 15/15] x86/msr: Change the function type of native_read_msr_safe() Xin Li (Intel)
2025-05-02 14:13 ` [PATCH v4 00/15] MSR code cleanup part one Michael Kelley
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