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[47.55.120.4]) by smtp.gmail.com with ESMTPSA id af79cd13be357-7e80b869d4bsm310283985a.24.2025.08.06.16.58.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Aug 2025 16:58:49 -0700 (PDT) Received: from jgg by wakko with local (Exim 4.97) (envelope-from ) id 1ujo1w-00000001sk1-2RDU; Wed, 06 Aug 2025 20:58:48 -0300 Date: Wed, 6 Aug 2025 20:58:48 -0300 From: Jason Gunthorpe To: Shyam Saini Cc: iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, virtualization@lists.linux.dev, will@kernel.org, jacob.pan@linux.microsoft.com, eric.auger@redhat.com, code@tyhicks.com, eahariha@linux.microsoft.com, vijayb@linux.microsoft.com, bboscaccy@linux.microsoft.com Subject: Re: [PATCH v3 3/3] arm-smmu: select suitable MSI IOVA Message-ID: <20250806235848.GD377696@ziepe.ca> References: <20250806215539.1240561-1-shyamsaini@linux.microsoft.com> <20250806215539.1240561-4-shyamsaini@linux.microsoft.com> Precedence: bulk X-Mailing-List: virtualization@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250806215539.1240561-4-shyamsaini@linux.microsoft.com> On Wed, Aug 06, 2025 at 02:55:39PM -0700, Shyam Saini wrote: > --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > @@ -3642,17 +3642,30 @@ static int arm_smmu_of_xlate(struct device *dev, > static void arm_smmu_get_resv_regions(struct device *dev, > struct list_head *head) > { > - struct iommu_resv_region *region; > int prot = IOMMU_WRITE | IOMMU_NOEXEC | IOMMU_MMIO; > > - region = iommu_alloc_resv_region(MSI_IOVA_BASE, MSI_IOVA_LENGTH, > - prot, IOMMU_RESV_SW_MSI, GFP_KERNEL); > - if (!region) > - return; > - > - list_add_tail(®ion->list, head); > + static const u64 msi_bases[] = { MSI_IOVA_BASE, MSI_IOVA_BASE2 }; > > iommu_dma_get_resv_regions(dev, head); > + > + /* > + * Use the first msi_base that does not intersect with a platform > + * reserved region. The SW MSI base selection is entirely arbitrary. > + */ > + for (int i = 0; i != ARRAY_SIZE(msi_bases); i++) { > + struct iommu_resv_region *region; > + > + if (resv_region_intersects(msi_bases[i], MSI_IOVA_LENGTH, head)) > + continue; > + > + region = iommu_alloc_resv_region(msi_bases[i], MSI_IOVA_LENGTH, prot, > + IOMMU_RESV_SW_MSI, GFP_KERNEL); > + if (!region) > + return; > + > + list_add_tail(®ion->list, head); > + return; > + } > } I think this whole series looks pretty good, but I would suggest to put this in a helper.. 'iommu_set_sw_msi()' perhaps, must be called after iommu_dma_get_resv_regions() Then maybe the constants can just be placed in the .c file inside the helper function. Jsaon