From: Juergen Gross <jgross@suse.com>
To: linux-kernel@vger.kernel.org, x86@kernel.org,
virtualization@lists.linux.dev
Cc: Juergen Gross <jgross@suse.com>,
Thomas Gleixner <tglx@kernel.org>, Ingo Molnar <mingo@redhat.com>,
Borislav Petkov <bp@alien8.de>,
Dave Hansen <dave.hansen@linux.intel.com>,
"H. Peter Anvin" <hpa@zytor.com>,
Ajay Kaher <ajay.kaher@broadcom.com>,
Alexey Makhalov <alexey.makhalov@broadcom.com>,
Broadcom internal kernel review list
<bcm-kernel-feedback-list@broadcom.com>
Subject: [PATCH v3 06/16] x86/msr: Move MSR trace calls one function level up
Date: Wed, 18 Feb 2026 09:21:23 +0100 [thread overview]
Message-ID: <20260218082133.400602-7-jgross@suse.com> (raw)
In-Reply-To: <20260218082133.400602-1-jgross@suse.com>
In order to prepare paravirt inlining of the MSR access instructions
move the calls of MSR trace functions one function level up.
Introduce {read|write}_msr[_safe]() helpers allowing to have common
definitions in msr.h doing the trace calls.
Signed-off-by: Juergen Gross <jgross@suse.com>
Reviewed-by: H. Peter Anvin (Intel) <hpa@zytor.com>
---
arch/x86/include/asm/msr.h | 102 ++++++++++++++++++++------------
arch/x86/include/asm/paravirt.h | 38 +++---------
2 files changed, 73 insertions(+), 67 deletions(-)
diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h
index 9c2ea29e12a9..71f41af11591 100644
--- a/arch/x86/include/asm/msr.h
+++ b/arch/x86/include/asm/msr.h
@@ -103,14 +103,7 @@ static __always_inline u64 native_rdmsrq(u32 msr)
static inline u64 native_read_msr(u32 msr)
{
- u64 val;
-
- val = __rdmsr(msr);
-
- if (tracepoint_enabled(read_msr))
- do_trace_read_msr(msr, val, 0);
-
- return val;
+ return __rdmsr(msr);
}
static inline int native_read_msr_safe(u32 msr, u64 *p)
@@ -123,8 +116,6 @@ static inline int native_read_msr_safe(u32 msr, u64 *p)
_ASM_EXTABLE_TYPE_REG(1b, 2b, EX_TYPE_RDMSR_SAFE, %[err])
: [err] "=r" (err), EAX_EDX_RET(val, low, high)
: "c" (msr));
- if (tracepoint_enabled(read_msr))
- do_trace_read_msr(msr, EAX_EDX_VAL(val, low, high), err);
*p = EAX_EDX_VAL(val, low, high);
@@ -135,9 +126,6 @@ static inline int native_read_msr_safe(u32 msr, u64 *p)
static inline void notrace native_write_msr(u32 msr, u64 val)
{
native_wrmsrq(msr, val);
-
- if (tracepoint_enabled(write_msr))
- do_trace_write_msr(msr, val, 0);
}
/* Can be uninlined because referenced by paravirt */
@@ -151,8 +139,6 @@ static inline int notrace native_write_msr_safe(u32 msr, u64 val)
: [err] "=a" (err)
: "c" (msr), "0" ((u32)val), "d" ((u32)(val >> 32))
: "memory");
- if (tracepoint_enabled(write_msr))
- do_trace_write_msr(msr, val, err);
return err;
}
@@ -173,59 +159,96 @@ static inline u64 native_read_pmc(int counter)
#include <asm/paravirt.h>
#else
#include <linux/errno.h>
+static __always_inline u64 read_msr(u32 msr)
+{
+ return native_read_msr(msr);
+}
+
+static __always_inline int read_msr_safe(u32 msr, u64 *p)
+{
+ return native_read_msr_safe(msr, p);
+}
+
+static __always_inline void write_msr(u32 msr, u64 val)
+{
+ native_write_msr(msr, val);
+}
+
+static __always_inline int write_msr_safe(u32 msr, u64 val)
+{
+ return native_write_msr_safe(msr, val);
+}
+
+static __always_inline u64 rdpmc(int counter)
+{
+ return native_read_pmc(counter);
+}
+
+#endif /* !CONFIG_PARAVIRT_XXL */
+
/*
* Access to machine-specific registers (available on 586 and better only)
* Note: the rd* operations modify the parameters directly (without using
* pointer indirection), this allows gcc to optimize better
*/
+#define rdmsrq(msr, val) \
+do { \
+ (val) = read_msr(msr); \
+ if (tracepoint_enabled(read_msr)) \
+ do_trace_read_msr(msr, val, 0); \
+} while (0)
+
#define rdmsr(msr, low, high) \
do { \
- u64 __val = native_read_msr((msr)); \
+ u64 __val; \
+ rdmsrq(msr, __val); \
(void)((low) = (u32)__val); \
(void)((high) = (u32)(__val >> 32)); \
} while (0)
-static inline void wrmsr(u32 msr, u32 low, u32 high)
+/* rdmsr with exception handling */
+static inline int rdmsrq_safe(u32 msr, u64 *p)
{
- native_write_msr(msr, (u64)high << 32 | low);
-}
+ int err;
-#define rdmsrq(msr, val) \
- ((val) = native_read_msr((msr)))
+ err = read_msr_safe(msr, p);
-static inline void wrmsrq(u32 msr, u64 val)
-{
- native_write_msr(msr, val);
-}
+ if (tracepoint_enabled(read_msr))
+ do_trace_read_msr(msr, *p, err);
-/* wrmsr with exception handling */
-static inline int wrmsrq_safe(u32 msr, u64 val)
-{
- return native_write_msr_safe(msr, val);
+ return err;
}
-/* rdmsr with exception handling */
#define rdmsr_safe(msr, low, high) \
({ \
u64 __val; \
- int __err = native_read_msr_safe((msr), &__val); \
+ int __err = rdmsrq_safe((msr), &__val); \
(*low) = (u32)__val; \
(*high) = (u32)(__val >> 32); \
__err; \
})
-static inline int rdmsrq_safe(u32 msr, u64 *p)
+static inline void wrmsrq(u32 msr, u64 val)
{
- return native_read_msr_safe(msr, p);
+ write_msr(msr, val);
+
+ if (tracepoint_enabled(write_msr))
+ do_trace_write_msr(msr, val, 0);
}
-static __always_inline u64 rdpmc(int counter)
+/* wrmsr with exception handling */
+static inline int wrmsrq_safe(u32 msr, u64 val)
{
- return native_read_pmc(counter);
-}
+ int err;
-#endif /* !CONFIG_PARAVIRT_XXL */
+ err = write_msr_safe(msr, val);
+
+ if (tracepoint_enabled(write_msr))
+ do_trace_write_msr(msr, val, err);
+
+ return err;
+}
/* Instruction opcode for WRMSRNS supported in binutils >= 2.40 */
#define ASM_WRMSRNS _ASM_BYTES(0x0f,0x01,0xc6)
@@ -242,6 +265,11 @@ static __always_inline void wrmsrns(u32 msr, u64 val)
: : "c" (msr), "a" ((u32)val), "d" ((u32)(val >> 32)));
}
+static inline void wrmsr(u32 msr, u32 low, u32 high)
+{
+ wrmsrq(msr, (u64)high << 32 | low);
+}
+
/*
* Dual u32 version of wrmsrq_safe():
*/
diff --git a/arch/x86/include/asm/paravirt.h b/arch/x86/include/asm/paravirt.h
index cdfe4007443e..6b3aed5c2309 100644
--- a/arch/x86/include/asm/paravirt.h
+++ b/arch/x86/include/asm/paravirt.h
@@ -150,46 +150,24 @@ static inline int paravirt_write_msr_safe(u32 msr, u64 val)
return PVOP_CALL2(int, pv_ops, cpu.write_msr_safe, msr, val);
}
-#define rdmsr(msr, val1, val2) \
-do { \
- u64 _l = paravirt_read_msr(msr); \
- val1 = (u32)_l; \
- val2 = _l >> 32; \
-} while (0)
-
-static __always_inline void wrmsr(u32 msr, u32 low, u32 high)
+static __always_inline u64 read_msr(u32 msr)
{
- paravirt_write_msr(msr, (u64)high << 32 | low);
+ return paravirt_read_msr(msr);
}
-#define rdmsrq(msr, val) \
-do { \
- val = paravirt_read_msr(msr); \
-} while (0)
-
-static inline void wrmsrq(u32 msr, u64 val)
+static __always_inline int read_msr_safe(u32 msr, u64 *p)
{
- paravirt_write_msr(msr, val);
+ return paravirt_read_msr_safe(msr, p);
}
-static inline int wrmsrq_safe(u32 msr, u64 val)
+static __always_inline void write_msr(u32 msr, u64 val)
{
- return paravirt_write_msr_safe(msr, val);
+ paravirt_write_msr(msr, val);
}
-/* rdmsr with exception handling */
-#define rdmsr_safe(msr, a, b) \
-({ \
- u64 _l; \
- int _err = paravirt_read_msr_safe((msr), &_l); \
- (*a) = (u32)_l; \
- (*b) = (u32)(_l >> 32); \
- _err; \
-})
-
-static __always_inline int rdmsrq_safe(u32 msr, u64 *p)
+static __always_inline int write_msr_safe(u32 msr, u64 val)
{
- return paravirt_read_msr_safe(msr, p);
+ return paravirt_write_msr_safe(msr, val);
}
static __always_inline u64 rdpmc(int counter)
--
2.53.0
next prev parent reply other threads:[~2026-02-18 8:22 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-02-18 8:21 [PATCH v3 00/16] x86/msr: Inline rdmsr/wrmsr instructions Juergen Gross
2026-02-18 8:21 ` Juergen Gross [this message]
2026-02-18 8:21 ` [PATCH v3 12/16] x86/paravirt: Split off MSR related hooks into new header Juergen Gross
2026-02-18 8:21 ` [PATCH v3 13/16] x86/paravirt: Prepare support of MSR instruction interfaces Juergen Gross
2026-02-18 8:21 ` [PATCH v3 14/16] x86/paravirt: Switch MSR access pv_ops functions to " Juergen Gross
2026-02-18 8:21 ` [PATCH v3 16/16] x86/paravirt: Use alternatives for MSR access with paravirt Juergen Gross
2026-02-18 13:49 ` kernel test robot
2026-02-18 15:49 ` Juergen Gross
2026-02-18 20:37 ` [PATCH v3 00/16] x86/msr: Inline rdmsr/wrmsr instructions H. Peter Anvin
2026-02-19 6:28 ` Jürgen Groß
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