Re: [PATCH v8 0/2] skip redundant sync IPIs when TLB flush sent them

[Lance Yang <lance.yang@linux.dev>]

On Tue, Mar 24, 2026 at 11:43:39AM -0700, Andrew Morton wrote:
>On Tue, 24 Mar 2026 16:52:36 +0800 Lance Yang <lance.yang@linux.dev> wrote:
>
>> Hi all,
>> 
>> When page table operations require synchronization with software/lockless
>> walkers, they call tlb_remove_table_sync_{one,rcu}() after flushing the
>> TLB (tlb->freed_tables or tlb->unshared_tables).
>> 
>> On architectures where the TLB flush already sends IPIs to all target CPUs,
>> the subsequent sync IPI broadcast is redundant. This is not only costly on
>> large systems where it disrupts all CPUs even for single-process page table
>> operations, but has also been reported to hurt RT workloads[1].
>> 
>> This series introduces tlb_table_flush_implies_ipi_broadcast() to check if
>> the prior TLB flush already provided the necessary synchronization. When
>> true, the sync calls can early-return.
>> 
>> A few cases rely on this synchronization:
>> 
>> 1) hugetlb PMD unshare[2]: The problem is not the freeing but the reuse
>>    of the PMD table for other purposes in the last remaining user after
>>    unsharing.
>> 
>> 2) khugepaged collapse[3]: Ensure no concurrent GUP-fast before collapsing
>>    and (possibly) freeing the page table / re-depositing it.
>> 
>> Two-step plan as David suggested[4]:
>> 
>> Step 1 (this series): Skip redundant sync when we're 100% certain the TLB
>> flush sent IPIs. INVLPGB is excluded because when supported, we cannot
>> guarantee IPIs were sent, keeping it clean and simple.
>> 
>> Step 2 (future work): Send targeted IPIs only to CPUs actually doing
>> software/lockless page table walks, benefiting all architectures.
>> 
>> Regarding Step 2, it obviously only applies to setups where Step 1 does not
>> apply: like x86 with INVLPGB or arm64. Step 2 work is ongoing; early
>> attempts showed ~3% GUP-fast overhead. Reducing the overhead requires more
>> work and tuning; it will be submitted separately once ready.
>> 
>> On a 64-core Intel x86 server, the CAL interrupt count in
>> /proc/interrupts dropped from 646,316 to 785 when collapsing a 20 GiB
>> range with this series applied.
>
>Well that's nice.
>
>Which other architectures could utilize this?

Thanks! RISC-V looks like a candidate, and if I get some time I'll dive
into it.

>
>> David Hildenbrand did the initial implementation. I built on his work and
>> relied on off-list discussions to push it further - thanks a lot David!
>>
>> ...
>>
>>  arch/x86/include/asm/tlb.h      | 18 +++++++++++++++++-
>>  arch/x86/include/asm/tlbflush.h |  2 ++
>>  arch/x86/kernel/smpboot.c       |  1 +
>>  arch/x86/mm/tlb.c               | 15 +++++++++++++++
>>  include/asm-generic/tlb.h       | 17 +++++++++++++++++
>>  mm/mmu_gather.c                 | 15 +++++++++++++++
>>  6 files changed, 67 insertions(+), 1 deletion(-)
>
>Can the x86 maintainers please review these changes?

Yes, an x86 review would be much appreciated, please!

After commit a37259732a7d ("x86/mm: Make MMU_GATHER_RCU_TABLE_FREE
unconditional"), tlb_remove_table_sync_one() is no longer a NOP, even on
native x86 without INVLPGB, so it ends up issuing a redundant IPI
broadcast.

Thanks,
Lance