From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp-out1.suse.de (smtp-out1.suse.de [195.135.223.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C99773C09E7 for ; Mon, 29 Jun 2026 06:57:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=195.135.223.130 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782716227; cv=none; b=XxaRthBQ40OtrYa0dKXwcNjsPLfVhmpot6EoaxrTEdt04T5snVxCF0SEPi1jgcIr6wFfnkPm5mhM4oIIkq9lPvmqsPsrYIFcJpKLPQ/AIj1utDcnF2pEA1Kz2WjVluQAPwCP6bQFPIPNKHcqZ6B2oG0yOCjKe1cMCT/2mPLdJg0= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782716227; c=relaxed/simple; bh=Oo1oaQ2ieE6bzbmK7r/V2eE+8JKDWzUKOzTIgZcpCN8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Uhr6THHzhLndfQupvEKzXaA4CVNflH6mF4exrURiFW9RnOP6IKTFI7bmOOZcKDLqsvEZh+lXYKMCXv6OUmrr65y70CzYC8ATF5UlodgqpV9iUEg8MnZDxMNQYevwLkwKjFk6T9hnMzPxQ3jfQlt0ez0TTroNxrmgLp4G/lTEFHs= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=suse.com; spf=pass smtp.mailfrom=suse.com; arc=none smtp.client-ip=195.135.223.130 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=suse.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=suse.com Received: from imap1.dmz-prg2.suse.org (imap1.dmz-prg2.suse.org [IPv6:2a07:de40:b281:104:10:150:64:97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by smtp-out1.suse.de (Postfix) with ESMTPS id E042271266; Mon, 29 Jun 2026 06:57:01 +0000 (UTC) Authentication-Results: smtp-out1.suse.de; none Received: from imap1.dmz-prg2.suse.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by imap1.dmz-prg2.suse.org (Postfix) with ESMTPS id 6F47E779A8; Mon, 29 Jun 2026 06:57:01 +0000 (UTC) Received: from dovecot-director2.suse.de ([2a07:de40:b281:106:10:150:64:167]) by imap1.dmz-prg2.suse.org with ESMTPSA id ktawGT0XQmp3QgAAD6G6ig (envelope-from ); Mon, 29 Jun 2026 06:57:01 +0000 From: Juergen Gross To: linux-kernel@vger.kernel.org, x86@kernel.org, virtualization@lists.linux.dev Cc: Juergen Gross , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Ajay Kaher , Alexey Makhalov , Broadcom internal kernel review list , Boris Ostrovsky , Josh Poimboeuf , Peter Zijlstra , xen-devel@lists.xenproject.org Subject: [PATCH v4 13/18] x86/paravirt: Split off MSR related hooks into new header Date: Mon, 29 Jun 2026 08:55:39 +0200 Message-ID: <20260629065544.3643253-14-jgross@suse.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260629065544.3643253-1-jgross@suse.com> References: <20260629065544.3643253-1-jgross@suse.com> Precedence: bulk X-Mailing-List: virtualization@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Rspamd-Pre-Result: action=no action; module=replies; Message is reply to one we originated X-Rspamd-Queue-Id: E042271266 X-Spam-Flag: NO X-Spam-Score: -4.00 X-Spam-Level: X-Rspamd-Action: no action X-Rspamd-Server: rspamd1.dmz-prg2.suse.org X-Rspamd-Pre-Result: action=no action; module=replies; Message is reply to one we originated X-Spamd-Result: default: False [-4.00 / 50.00]; REPLY(-4.00)[] Move the WRMSR, RDMSR and RDPMC related parts of paravirt.h and paravirt_types.h into a new header file paravirt-msr.h. Switch all moved helper functions to __always_inline. Signed-off-by: Juergen Gross --- V3: - new patch V4: - always use __always_inline --- arch/x86/include/asm/msr.h | 2 +- arch/x86/include/asm/paravirt-msr.h | 56 +++++++++++++++++++++++++++ arch/x86/include/asm/paravirt.h | 55 -------------------------- arch/x86/include/asm/paravirt_types.h | 13 ------- arch/x86/kernel/paravirt.c | 14 ++++--- arch/x86/xen/enlighten_pv.c | 11 +++--- tools/objtool/check.c | 1 + 7 files changed, 73 insertions(+), 79 deletions(-) create mode 100644 arch/x86/include/asm/paravirt-msr.h diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h index 6a8af80305d1..b13b4a93673e 100644 --- a/arch/x86/include/asm/msr.h +++ b/arch/x86/include/asm/msr.h @@ -323,7 +323,7 @@ static inline u64 native_read_pmc(int counter) } #ifdef CONFIG_PARAVIRT_XXL -#include +#include #else static __always_inline u64 read_msr(u32 msr) { diff --git a/arch/x86/include/asm/paravirt-msr.h b/arch/x86/include/asm/paravirt-msr.h new file mode 100644 index 000000000000..3e31648316a8 --- /dev/null +++ b/arch/x86/include/asm/paravirt-msr.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef _ASM_X86_PARAVIRT_MSR_H +#define _ASM_X86_PARAVIRT_MSR_H + +#include + +struct pv_msr_ops { + /* Unsafe MSR operations. These will warn or panic on failure. */ + u64 (*read_msr)(u32 msr); + void (*write_msr)(u32 msr, u64 val); + + /* Safe MSR operations. Returns 0 or -EIO. */ + int (*read_msr_safe)(u32 msr, u64 *val); + int (*write_msr_safe)(u32 msr, u64 val); + + u64 (*read_pmc)(int counter); +} __no_randomize_layout; + +extern struct pv_msr_ops pv_ops_msr; + +static __always_inline u64 read_msr(u32 msr) +{ + return PVOP_CALL1(u64, pv_ops_msr, read_msr, msr); +} + +static __always_inline void write_msr(u32 msr, u64 val) +{ + PVOP_VCALL2(pv_ops_msr, write_msr, msr, val); +} + +static __always_inline void write_msrns(u32 msr, u64 val) +{ + PVOP_VCALL2(pv_ops_msr, write_msr, msr, val); +} + +static __always_inline int read_msr_safe(u32 msr, u64 *val) +{ + return PVOP_CALL2(int, pv_ops_msr, read_msr_safe, msr, val); +} + +static __always_inline int write_msr_safe(u32 msr, u64 val) +{ + return PVOP_CALL2(int, pv_ops_msr, write_msr_safe, msr, val); +} + +static __always_inline int write_msrns_safe(u32 msr, u64 val) +{ + return PVOP_CALL2(int, pv_ops_msr, write_msr_safe, msr, val); +} + +static __always_inline u64 rdpmc(int counter) +{ + return PVOP_CALL1(u64, pv_ops_msr, read_pmc, counter); +} + +#endif /* _ASM_X86_PARAVIRT_MSR_H */ diff --git a/arch/x86/include/asm/paravirt.h b/arch/x86/include/asm/paravirt.h index b0c740316cf7..eb16d55f94d3 100644 --- a/arch/x86/include/asm/paravirt.h +++ b/arch/x86/include/asm/paravirt.h @@ -130,61 +130,6 @@ static inline void __write_cr4(unsigned long x) PVOP_VCALL1(pv_ops, cpu.write_cr4, x); } -static inline u64 paravirt_read_msr(u32 msr) -{ - return PVOP_CALL1(u64, pv_ops, cpu.read_msr, msr); -} - -static inline void paravirt_write_msr(u32 msr, u64 val) -{ - PVOP_VCALL2(pv_ops, cpu.write_msr, msr, val); -} - -static inline int paravirt_read_msr_safe(u32 msr, u64 *val) -{ - return PVOP_CALL2(int, pv_ops, cpu.read_msr_safe, msr, val); -} - -static inline int paravirt_write_msr_safe(u32 msr, u64 val) -{ - return PVOP_CALL2(int, pv_ops, cpu.write_msr_safe, msr, val); -} - -static __always_inline u64 read_msr(u32 msr) -{ - return paravirt_read_msr(msr); -} - -static inline void write_msr(u32 msr, u64 val) -{ - paravirt_write_msr(msr, val); -} - -static __always_inline void write_msrns(u32 msr, u64 val) -{ - paravirt_write_msr(msr, val); -} - -static inline int write_msr_safe(u32 msr, u64 val) -{ - return paravirt_write_msr_safe(msr, val); -} - -static __always_inline int write_msrns_safe(u32 msr, u64 val) -{ - return paravirt_write_msr_safe(msr, val); -} - -static __always_inline int read_msr_safe(u32 msr, u64 *p) -{ - return paravirt_read_msr_safe(msr, p); -} - -static __always_inline u64 rdpmc(int counter) -{ - return PVOP_CALL1(u64, pv_ops, cpu.read_pmc, counter); -} - static inline void paravirt_alloc_ldt(struct desc_struct *ldt, unsigned entries) { PVOP_VCALL2(pv_ops, cpu.alloc_ldt, ldt, entries); diff --git a/arch/x86/include/asm/paravirt_types.h b/arch/x86/include/asm/paravirt_types.h index b4c4a23e77a1..2459163fa196 100644 --- a/arch/x86/include/asm/paravirt_types.h +++ b/arch/x86/include/asm/paravirt_types.h @@ -58,19 +58,6 @@ struct pv_cpu_ops { void (*cpuid)(unsigned int *eax, unsigned int *ebx, unsigned int *ecx, unsigned int *edx); - /* Unsafe MSR operations. These will warn or panic on failure. */ - u64 (*read_msr)(u32 msr); - void (*write_msr)(u32 msr, u64 val); - - /* - * Safe MSR operations. - * Returns 0 or -EIO. - */ - int (*read_msr_safe)(u32 msr, u64 *val); - int (*write_msr_safe)(u32 msr, u64 val); - - u64 (*read_pmc)(int counter); - void (*start_context_switch)(struct task_struct *prev); void (*end_context_switch)(struct task_struct *next); #endif diff --git a/arch/x86/kernel/paravirt.c b/arch/x86/kernel/paravirt.c index 00b59d774389..739dbfd8aadf 100644 --- a/arch/x86/kernel/paravirt.c +++ b/arch/x86/kernel/paravirt.c @@ -110,11 +110,6 @@ struct paravirt_patch_template pv_ops = { .cpu.read_cr0 = native_read_cr0, .cpu.write_cr0 = native_write_cr0, .cpu.write_cr4 = native_write_cr4, - .cpu.read_msr = native_read_msr, - .cpu.write_msr = native_write_msr, - .cpu.read_msr_safe = native_read_msr_safe, - .cpu.write_msr_safe = native_write_msr_safe, - .cpu.read_pmc = native_read_pmc, .cpu.load_tr_desc = native_load_tr_desc, .cpu.set_ldt = native_set_ldt, .cpu.load_gdt = native_load_gdt, @@ -212,6 +207,15 @@ struct paravirt_patch_template pv_ops = { }; #ifdef CONFIG_PARAVIRT_XXL +struct pv_msr_ops pv_ops_msr = { + .read_msr = native_read_msr, + .write_msr = native_write_msr, + .read_msr_safe = native_read_msr_safe, + .write_msr_safe = native_write_msr_safe, + .read_pmc = native_read_pmc, +}; +EXPORT_SYMBOL(pv_ops_msr); + NOKPROBE_SYMBOL(native_load_idt); #endif diff --git a/arch/x86/xen/enlighten_pv.c b/arch/x86/xen/enlighten_pv.c index 2c64b388f616..bf81e84ff261 100644 --- a/arch/x86/xen/enlighten_pv.c +++ b/arch/x86/xen/enlighten_pv.c @@ -1360,11 +1360,6 @@ asmlinkage __visible void __init xen_start_kernel(struct start_info *si) pv_ops.cpu.read_cr0 = xen_read_cr0; pv_ops.cpu.write_cr0 = xen_write_cr0; pv_ops.cpu.write_cr4 = xen_write_cr4; - pv_ops.cpu.read_msr = xen_read_msr; - pv_ops.cpu.write_msr = xen_write_msr; - pv_ops.cpu.read_msr_safe = xen_read_msr_safe; - pv_ops.cpu.write_msr_safe = xen_write_msr_safe; - pv_ops.cpu.read_pmc = xen_read_pmc; pv_ops.cpu.load_tr_desc = paravirt_nop; pv_ops.cpu.set_ldt = xen_set_ldt; pv_ops.cpu.load_gdt = xen_load_gdt; @@ -1385,6 +1380,12 @@ asmlinkage __visible void __init xen_start_kernel(struct start_info *si) pv_ops.cpu.start_context_switch = xen_start_context_switch; pv_ops.cpu.end_context_switch = xen_end_context_switch; + pv_ops_msr.read_msr = xen_read_msr; + pv_ops_msr.write_msr = xen_write_msr; + pv_ops_msr.read_msr_safe = xen_read_msr_safe; + pv_ops_msr.write_msr_safe = xen_write_msr_safe; + pv_ops_msr.read_pmc = xen_read_pmc; + xen_init_irq_ops(); /* diff --git a/tools/objtool/check.c b/tools/objtool/check.c index 10b18cf9c360..2c91fcff77f4 100644 --- a/tools/objtool/check.c +++ b/tools/objtool/check.c @@ -525,6 +525,7 @@ static struct { } pv_ops_tables[] = { { .name = "pv_ops", }, { .name = "pv_ops_lock", }, + { .name = "pv_ops_msr", }, { .name = NULL, .idx_off = -1 } }; -- 2.54.0