From: Juergen Gross <jgross@suse.com>
To: linux-kernel@vger.kernel.org, x86@kernel.org,
virtualization@lists.linux.dev
Cc: Juergen Gross <jgross@suse.com>,
Ajay Kaher <ajay.kaher@broadcom.com>,
Alexey Makhalov <alexey.makhalov@broadcom.com>,
Broadcom internal kernel review list
<bcm-kernel-feedback-list@broadcom.com>,
Thomas Gleixner <tglx@kernel.org>, Ingo Molnar <mingo@redhat.com>,
Borislav Petkov <bp@alien8.de>,
Dave Hansen <dave.hansen@linux.intel.com>,
"H. Peter Anvin" <hpa@zytor.com>
Subject: [PATCH v4 14/18] x86/paravirt: Prepare support of MSR instruction interfaces
Date: Mon, 29 Jun 2026 08:55:40 +0200 [thread overview]
Message-ID: <20260629065544.3643253-15-jgross@suse.com> (raw)
In-Reply-To: <20260629065544.3643253-1-jgross@suse.com>
Make the paravirt callee-save infrastructure more generic by allowing
arbitrary register interfaces via prologue and epilogue helper macros.
Signed-off-by: Juergen Gross <jgross@suse.com>
---
V3:
- carved out from patch 5 of V1
---
arch/x86/include/asm/paravirt_types.h | 43 ++++++++++++++---------
arch/x86/include/asm/qspinlock_paravirt.h | 4 +--
2 files changed, 29 insertions(+), 18 deletions(-)
diff --git a/arch/x86/include/asm/paravirt_types.h b/arch/x86/include/asm/paravirt_types.h
index 2459163fa196..740ea819bbab 100644
--- a/arch/x86/include/asm/paravirt_types.h
+++ b/arch/x86/include/asm/paravirt_types.h
@@ -448,27 +448,38 @@ extern struct paravirt_patch_template pv_ops;
#define PV_SAVE_ALL_CALLER_REGS "pushl %ecx;"
#define PV_RESTORE_ALL_CALLER_REGS "popl %ecx;"
#else
+/* Save and restore caller-save registers, except %rax, %rcx and %rdx. */
+#define PV_SAVE_COMMON_CALLER_REGS \
+ "push %rsi;" \
+ "push %rdi;" \
+ "push %r8;" \
+ "push %r9;" \
+ "push %r10;" \
+ "push %r11;"
+
+#define PV_RESTORE_COMMON_CALLER_REGS \
+ "pop %r11;" \
+ "pop %r10;" \
+ "pop %r9;" \
+ "pop %r8;" \
+ "pop %rdi;" \
+ "pop %rsi;"
+
/* save and restore all caller-save registers, except return value */
#define PV_SAVE_ALL_CALLER_REGS \
"push %rcx;" \
"push %rdx;" \
- "push %rsi;" \
- "push %rdi;" \
- "push %r8;" \
- "push %r9;" \
- "push %r10;" \
- "push %r11;"
+ PV_SAVE_COMMON_CALLER_REGS
+
#define PV_RESTORE_ALL_CALLER_REGS \
- "pop %r11;" \
- "pop %r10;" \
- "pop %r9;" \
- "pop %r8;" \
- "pop %rdi;" \
- "pop %rsi;" \
+ PV_RESTORE_COMMON_CALLER_REGS \
"pop %rdx;" \
"pop %rcx;"
#endif
+#define PV_PROLOGUE_ALL(func) PV_SAVE_ALL_CALLER_REGS
+#define PV_EPILOGUE_ALL(func) PV_RESTORE_ALL_CALLER_REGS
+
/*
* Generate a thunk around a function which saves all caller-save
* registers except for the return value. This allows C functions to
@@ -482,7 +493,7 @@ extern struct paravirt_patch_template pv_ops;
* functions.
*/
#define PV_THUNK_NAME(func) "__raw_callee_save_" #func
-#define __PV_CALLEE_SAVE_REGS_THUNK(func, section) \
+#define __PV_CALLEE_SAVE_REGS_THUNK(func, section, helper) \
extern typeof(func) __raw_callee_save_##func; \
\
asm(".pushsection " section ", \"ax\";" \
@@ -492,16 +503,16 @@ extern struct paravirt_patch_template pv_ops;
PV_THUNK_NAME(func) ":" \
ASM_ENDBR \
FRAME_BEGIN \
- PV_SAVE_ALL_CALLER_REGS \
+ PV_PROLOGUE_##helper(func) \
"call " #func ";" \
- PV_RESTORE_ALL_CALLER_REGS \
+ PV_EPILOGUE_##helper(func) \
FRAME_END \
ASM_RET \
".size " PV_THUNK_NAME(func) ", .-" PV_THUNK_NAME(func) ";" \
".popsection")
#define PV_CALLEE_SAVE_REGS_THUNK(func) \
- __PV_CALLEE_SAVE_REGS_THUNK(func, ".text")
+ __PV_CALLEE_SAVE_REGS_THUNK(func, ".text", ALL)
/* Get a reference to a callee-save function */
#define PV_CALLEE_SAVE(func) \
diff --git a/arch/x86/include/asm/qspinlock_paravirt.h b/arch/x86/include/asm/qspinlock_paravirt.h
index 0a985784be9b..002b17f0735e 100644
--- a/arch/x86/include/asm/qspinlock_paravirt.h
+++ b/arch/x86/include/asm/qspinlock_paravirt.h
@@ -14,7 +14,7 @@ void __lockfunc __pv_queued_spin_unlock_slowpath(struct qspinlock *lock, u8 lock
*/
#ifdef CONFIG_64BIT
-__PV_CALLEE_SAVE_REGS_THUNK(__pv_queued_spin_unlock_slowpath, ".spinlock.text");
+__PV_CALLEE_SAVE_REGS_THUNK(__pv_queued_spin_unlock_slowpath, ".spinlock.text", ALL);
#define __pv_queued_spin_unlock __pv_queued_spin_unlock
/*
@@ -61,7 +61,7 @@ DEFINE_ASM_FUNC(__raw_callee_save___pv_queued_spin_unlock,
#else /* CONFIG_64BIT */
extern void __lockfunc __pv_queued_spin_unlock(struct qspinlock *lock);
-__PV_CALLEE_SAVE_REGS_THUNK(__pv_queued_spin_unlock, ".spinlock.text");
+__PV_CALLEE_SAVE_REGS_THUNK(__pv_queued_spin_unlock, ".spinlock.text", ALL);
#endif /* CONFIG_64BIT */
#endif
--
2.54.0
next prev parent reply other threads:[~2026-06-29 6:57 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-29 6:55 [PATCH v4 00/18] x86/msr: Inline rdmsr/wrmsr instructions Juergen Gross
2026-06-29 6:55 ` [PATCH v4 05/18] x86/msr: Move MSR trace calls one function level up Juergen Gross
2026-06-29 6:55 ` [PATCH v4 09/18] x86/msr: Make wrmsrns() a first class citizen Juergen Gross
2026-06-29 6:55 ` [PATCH v4 13/18] x86/paravirt: Split off MSR related hooks into new header Juergen Gross
2026-06-29 6:55 ` Juergen Gross [this message]
2026-06-29 6:55 ` [PATCH v4 15/18] x86/paravirt: Switch MSR access pv_ops functions to instruction interfaces Juergen Gross
2026-06-29 6:55 ` [PATCH v4 17/18] x86/paravirt: Use alternatives for MSR access with paravirt Juergen Gross
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