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Thu, 12 Nov 2026 22:09:43 -0800 (PST) X-Received: by 2002:a05:600c:620f:b0:4a1:80d8:aed5 with SMTP id 5b1f17b1804b1-4bb55a3e3abmr26930375e9.6.1794550182655; Thu, 12 Nov 2026 22:09:42 -0800 (PST) Received: from redhat.com ([2a0d:6fc0:1511:2900:ff37:b35c:a97:952d]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4bb55af1c5fsm33039755e9.12.2026.11.12.22.09.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Nov 2026 22:09:41 -0800 (PST) Date: Fri, 13 Nov 2026 01:09:39 -0500 From: "Michael S. Tsirkin" To: zhaoguohan@kylinos.cn Cc: bp@alien8.de, dave.hansen@linux.intel.com, eperezma@redhat.com, hpa@zytor.com, jasowang@redhat.com, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, mingo@redhat.com, netdev@vger.kernel.org, tglx@kernel.org, virtualization@lists.linux.dev, x86@kernel.org Subject: Re: [PATCH RFC] vhost: set dirty log bits without pinning pages on x86 Message-ID: <20261113010007-mutt-send-email-mst@kernel.org> References: <20261113012937.40818-1-zhaoguohan@kylinos.cn> X-Mailing-List: virtualization@lists.linux.dev List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 In-Reply-To: <20261113012937.40818-1-zhaoguohan@kylinos.cn> X-Mimecast-Spam-Score: 0 X-Mimecast-MFC-PROC-ID: OdiDAE414JYYQPLhfJvt3dDg4G7TgTQcTl187xAC6UE_1794550183 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Fri, Nov 13, 2026 at 09:29:37AM +0800, zhaoguohan@kylinos.cn wrote: > On Thu, Nov 12, 2026 at 05:53:47AM -0500, Michael S. Tsirkin wrote: > > vhost had a TODO to replace page pinning with a version > > of set_bit that works on userspace memory, since forever. > > > > It is really best to avoid GUP on fast path entirely. > > Implement set_user_bit and use it in vhost, to do just that. > [...] > > lightly tested. pls test and resubmit with your tool. > > Thanks, this is much simpler than my version. Two comments on > set_bit_user() before I resubmit: > > > + int __err = 0; \ > > + __uaccess_begin(); \ > > + asm volatile("\n" \ > > + "1: " LOCK_PREFIX "orb %[mask], %[ptr]\n" \ > > + "2:\n" \ > > + _ASM_EXTABLE_TYPE_REG(1b, 2b, EX_TYPE_EFAULT_REG, \ > > + %[errout]) \ > > + : [errout] "=r" (__err), \ > > + [ptr] "+m" (*(u8 __user *)(addr)) \ > > errout is only written on the fixup path, so it needs "+r", as in > __try_cmpxchg_user_asm(). With "=r" gcc drops the initialisation; here > (gcc 13.3, x86_64_defconfig) it even shares a register with mask: ah, subtle > > 1a3: lock or %dl,(%rax) > 1a9: test %edx,%edx > 1ab: jne 1bd > ... > 1bd: mov $0xfffffff2,%eax > > so every call returns -EFAULT, and log_write() stops after the first > page. > > > + __uaccess_begin(); \ > > No access_ok() here. vhost checks the log range when it is set up and > I couldn't find a way around that, but GUP used to reject kernel > addresses by itself. just a side effect of the api, unintentional. > user_access_begin() would keep the check (and the > nospec barrier) local. To expand on why is that not needed, but feel free to dispute - addresses all pre-validated - there is no possible gadget here, it's a write, writes are not speculated - lock prefix so no speculation anyway > Something like this, build-tested on x86_64 and > i386 only: > > diff --git a/arch/x86/include/asm/uaccess.h b/arch/x86/include/asm/uaccess.h > --- a/arch/x86/include/asm/uaccess.h > +++ b/arch/x86/include/asm/uaccess.h > @@ -597,19 +597,23 @@ _label: \ > /* set_bit() on a byte of user memory; returns -EFAULT on fault. */ > #define set_bit_user(nr, addr) \ > ({ \ > - int __err = 0; \ > - __uaccess_begin(); \ > - asm volatile("\n" \ > - "1: " LOCK_PREFIX "orb %[mask], %[ptr]\n" \ > - "2:\n" \ > - _ASM_EXTABLE_TYPE_REG(1b, 2b, EX_TYPE_EFAULT_REG, \ > - %[errout]) \ > - : [errout] "=r" (__err), \ > - [ptr] "+m" (*(u8 __user *)(addr)) \ > - : [mask] "q" ((unsigned char)BIT(nr)) \ > - : "memory", "cc"); \ > - __uaccess_end(); \ > - __err ? -EFAULT : 0; \ > + u8 __user *__p = (addr); \ > + int __err = -EFAULT; \ > + if (user_access_begin(__p, sizeof(*__p))) { \ > + __err = 0; \ > + asm volatile("\n" \ > + "1: " LOCK_PREFIX "orb %[mask], %[ptr]\n" \ > + "2:\n" \ > + _ASM_EXTABLE_TYPE_REG(1b, 2b, \ > + EX_TYPE_EFAULT_REG, \ > + %[errout]) \ > + : [errout] "+r" (__err), \ > + [ptr] "+m" (*__p) \ > + : [mask] "q" ((unsigned char)BIT(nr)) \ > + : "memory", "cc"); \ > + user_access_end(); \ > + } \ > + __err; \ > }) > > /* > > If this looks right, I'll fold it in, run my test in a VM and resubmit > with the test as a second patch. > > Thanks, > Khan