From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jeremy Fitzhardinge Subject: Re: how set_pte_at()'s vaddr and ptep args relate Date: Wed, 08 Nov 2006 15:25:53 -0800 Message-ID: <45526781.9000909@goop.org> References: Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: virtualization-bounces@lists.osdl.org Errors-To: virtualization-bounces@lists.osdl.org To: Keir Fraser Cc: Chris Wright , Virtualization Mailing List List-Id: virtualization@lists.linuxfoundation.org Keir Fraser wrote: > Another > factoid I discovered at the same meeting is that the CPU may cache partial > page walks. So, for example, just because you 'detach' a page table from a > page-directory entry, doesn't mean that page table won't be accessed on > future hardware TLB fills. > = Do you know if these intermediate TLB entries are level-sensitive? Ie, = if you have a linear pagetable mapping where the pagetable points back = to itself, will that result in multiple TLB entries for the pmd pages = (pmd as pmd, and pmd as pte)? J