From mboxrd@z Thu Jan 1 00:00:00 1970 From: "H. Peter Anvin" Subject: Re: [PATCH 0/4] i386 - pte update optimizations Date: Thu, 12 Apr 2007 18:25:05 -0700 Message-ID: <461EDBF1.4080904@zytor.com> References: <200704120530.l3C5UGbv022814@zach-dev.vmware.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: In-Reply-To: <200704120530.l3C5UGbv022814@zach-dev.vmware.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: virtualization-bounces@lists.linux-foundation.org Errors-To: virtualization-bounces@lists.linux-foundation.org To: Zachary Amsden Cc: Andrew Morton , Andi Kleen , Virtualization Mailing List , Chris Wright , David Rientjes , Hugh Dickins , Linux Kernel Mailing List List-Id: virtualization@lists.linuxfoundation.org Zachary Amsden wrote: > Some PTE optimizations for native and paravirt-ops kernels; this > provides a huge win for shadow mode hypervisors and gets rid of > some unnecessary atomic instructions in native kernels, saving > even more on UP by getting rid of implicit LOCK on xchg instruction. You do know that P6 and higher don't do locked bus references as long as = the value is in the cache, right? -hpa