From: Thomas Gleixner <tglx@linutronix.de>
To: Adrian Hunter <adrian.hunter@intel.com>,
Peter Zijlstra <peterz@infradead.org>
Cc: "kvm@vger.kernel.org" <kvm@vger.kernel.org>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Dave Hansen <dave.hansen@linux.intel.com>,
"virtualization@lists.linux-foundation.org"
<virtualization@lists.linux-foundation.org>,
H Peter Anvin <hpa@zytor.com>, Jiri Olsa <jolsa@redhat.com>,
"Hall, Christopher S" <christopher.s.hall@intel.com>,
"sthemmin@microsoft.com" <sthemmin@microsoft.com>,
"x86@kernel.org" <x86@kernel.org>,
"pv-drivers@vmware.com" <pv-drivers@vmware.com>,
Ingo Molnar <mingo@redhat.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Leo Yan <leo.yan@linaro.org>,
Arnaldo Carvalho de Melo <acme@kernel.org>,
Borislav Petkov <bp@alien8.de>,
"jgross@suse.com" <jgross@suse.com>,
Mathieu Poirier <mathieu.poirier@linaro.org>,
"seanjc@google.com" <seanjc@google.com>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"Andrew.Cooper3@citrix.com" <Andrew.Cooper3@citrix.com>,
"pbonzini@redhat.com" <pbonzini@redhat.com>
Subject: Re: [PATCH V2 03/11] perf/x86: Add support for TSC in nanoseconds as a perf event clock
Date: Mon, 25 Apr 2022 19:05:58 +0200 [thread overview]
Message-ID: <87fsm114ax.ffs@tglx> (raw)
In-Reply-To: <ff1e190a-95e6-e2a6-dc01-a46f7ffd2162@intel.com>
On Mon, Apr 25 2022 at 16:15, Adrian Hunter wrote:
> On 25/04/22 12:32, Thomas Gleixner wrote:
>> It's hillarious, that we still cling to this pvclock abomination, while
>> we happily expose TSC deadline timer to the guest. TSC virt scaling was
>> implemented in hardware for a reason.
>
> So you are talking about changing VMX TCS Offset on every VM-Entry to try to hide
> the time jumps when the VM is scheduled out? Or neglect that and just let the time
> jumps happen?
>
> If changing VMX TCS Offset, how can TSC be kept consistent between each VCPU i.e.
> wouldn't that mean each VCPU has to have the same VMX TSC Offset?
Obviously so. That's the only thing which makes sense, no?
Thanks,
tglx
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next prev parent reply other threads:[~2022-04-25 17:06 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20220214110914.268126-1-adrian.hunter@intel.com>
[not found] ` <20220214110914.268126-4-adrian.hunter@intel.com>
[not found] ` <YiIXFmA4vpcTSk2L@hirez.programming.kicks-ass.net>
[not found] ` <853ce127-25f0-d0fe-1d8f-0b0dd4f3ce71@intel.com>
2022-03-07 9:50 ` [PATCH V2 03/11] perf/x86: Add support for TSC in nanoseconds as a perf event clock Peter Zijlstra
2022-03-07 10:06 ` Juergen Gross via Virtualization
2022-03-07 10:38 ` Peter Zijlstra
2022-03-07 10:58 ` Juergen Gross via Virtualization
[not found] ` <30383f92-59cb-2875-1e1b-ff1a0eacd235@intel.com>
2022-03-07 14:42 ` Peter Zijlstra
[not found] ` <013b5425-2a60-e4d4-b846-444a576f2b28@intel.com>
[not found] ` <6f07a7d4e1ad4440bf6c502c8cb6c2ed@intel.com>
[not found] ` <c3e1842b-79c3-634a-3121-938b5160ca4c@intel.com>
[not found] ` <50fd2671-6070-0eba-ea68-9df9b79ccac3@intel.com>
2022-04-25 9:32 ` Thomas Gleixner
[not found] ` <ff1e190a-95e6-e2a6-dc01-a46f7ffd2162@intel.com>
2022-04-25 17:05 ` Thomas Gleixner [this message]
[not found] ` <c8033229-97a0-3e4c-66d5-74c0d1d4e15c@intel.com>
2022-04-27 23:10 ` Thomas Gleixner
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