From mboxrd@z Thu Jan 1 00:00:00 1970 From: Andy Lutomirski Subject: Re: Standardizing an MSR or other hypercall to get an RNG seed? Date: Thu, 18 Sep 2014 14:35:28 -0700 Message-ID: References: <5b9c7dcde3824e49a25f3ee00844b868@BY2PR0301MB0711.namprd03.prod.outlook.com> <541B13B8.1020006@redhat.com> <1969371640.51211843.1411066715223.JavaMail.zimbra@redhat.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: virtualization-bounces@lists.linux-foundation.org Errors-To: virtualization-bounces@lists.linux-foundation.org To: "Nakajima, Jun" Cc: Mathew John , Theodore Ts'o , John Starks , kvm list , Gleb Natapov , Niels Ferguson , Linux Virtualization , David Hepkin , "H. Peter Anvin" , Jake Oshins , Paolo Bonzini List-Id: virtualization@lists.linuxfoundation.org On Thu, Sep 18, 2014 at 2:21 PM, Nakajima, Jun wrote: > On Thu, Sep 18, 2014 at 12:07 PM, Andy Lutomirski wrote: > >> Might Intel be willing to extend that range to 0x40000000 - >> 0x400fffff? And would Microsoft be okay with using this mechanism for >> discovery? > > So, for CPUID, the SDM (Table 3-17. Information Returned by CPUID) says today: > "No existing or future CPU will return processor identification or > feature information if the initial EAX value is in the range 40000000H > to 4FFFFFFFH." > > We can define a cross-VM CPUID range from there. The CPUID can return > the index of the MSR if needed. Right, sorry. I was looking at this sentence in SDM Volume 3 Section 35.1: MSR address range between 40000000H - 400000FFH is marked as a specially reserved range. All existing and future processors will not implement any features using any MSR in this range. That's not really a large enough range for us to reserve an MSR for this. However, KVM, is already using MSRs outside that range: it uses 0x4b564d00-0x4b564d04 or so. I wonder whether KVM got confused by the differing ranges for cpuid leaves and MSR indices. Any chance that Intel could reserve a larger range to include the KVM MSRs? It would also be easier if the MSR indices for cross-HV features were constants. Thanks, Andy