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Wed, 12 Nov 2025 20:39:14 -0500 X-MC-Unique: fUfLTIZSPE24s4BrvPuQOA-1 X-Mimecast-MFC-AGG-ID: fUfLTIZSPE24s4BrvPuQOA_1762997952 Received: from mx-prod-int-01.mail-002.prod.us-west-2.aws.redhat.com (mx-prod-int-01.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.4]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx-prod-mc-06.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id 43DEE18007F2; Thu, 13 Nov 2025 01:39:10 +0000 (UTC) Received: from fedora (unknown [10.72.116.134]) by mx-prod-int-01.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id 753CF30044E0; Thu, 13 Nov 2025 01:39:01 +0000 (UTC) Date: Thu, 13 Nov 2025 09:38:56 +0800 From: Ming Lei To: "Guo, Wangyang" Cc: Andrew Morton , Thomas Gleixner , Keith Busch , Jens Axboe , Christoph Hellwig , Sagi Grimberg , linux-kernel@vger.kernel.org, linux-nvme@lists.infradead.org, virtualization@lists.linux-foundation.org, linux-block@vger.kernel.org, Tianyou Li , Tim Chen , Dan Liang Subject: Re: [PATCH RESEND] lib/group_cpus: make group CPU cluster aware Message-ID: References: <20251111020608.1501543-1-wangyang.guo@intel.com> Precedence: bulk X-Mailing-List: virtualization@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.4 On Wed, Nov 12, 2025 at 11:02:47AM +0800, Guo, Wangyang wrote: > On 11/11/2025 8:08 PM, Ming Lei wrote: > > On Tue, Nov 11, 2025 at 01:31:04PM +0800, Guo, Wangyang wrote: > > > On 11/11/2025 11:25 AM, Ming Lei wrote: > > > > On Tue, Nov 11, 2025 at 10:06:08AM +0800, Wangyang Guo wrote: > > > > > As CPU core counts increase, the number of NVMe IRQs may be smaller than > > > > > the total number of CPUs. This forces multiple CPUs to share the same > > > > > IRQ. If the IRQ affinity and the CPU’s cluster do not align, a > > > > > performance penalty can be observed on some platforms. > > > > > > > > Can you add details why/how CPU cluster isn't aligned with IRQ > > > > affinity? And how performance penalty is caused? > > > > > > Intel Xeon E platform packs 4 CPU cores as 1 module (cluster) and share the > > > L2 cache. Let's say, if there are 40 CPUs in 1 NUMA domain and 11 IRQs to > > > dispatch. The existing algorithm will map first 7 IRQs each with 4 CPUs and > > > remained 4 IRQs each with 3 CPUs each. The last 4 IRQs may have cross > > > cluster issue. For example, the 9th IRQ which pinned to CPU32, then for > > > CPU31, it will have cross L2 memory access. > > > > > > CPUs sharing L2 usually have small number, and it is common to see one queue > > mapping includes CPUs from different L2. > > > > So how much does crossing L2 hurt IO perf? > We see 15%+ performance difference in FIO libaio/randread/bs=8k. As I mentioned, it is common to see CPUs crossing L2 in same group, but why does it make a difference here? You mentioned just some platforms are affected. > > They still should share same L3 cache, and cpus_share_cache() should be > > true when the IO completes on the CPU which belong to different L2 with the > > submission CPU, and remote completion via IPI won't be triggered. > Yes, remote IPI not triggered. OK, in my test on AMD zen4, NVMe performance can be dropped to 1/2 - 1/3 if remote IPI is triggered in case of crossing L3, which is understandable. I will check if topo cluster can cover L3, if yes, the patch still can be simplified a lot by introducing sub-node spread by changing build_node_to_cpumask() and adding nr_sub_nodes. Thanks, Ming