From: Ingo Molnar <mingo@kernel.org>
To: "Ahmed S. Darwish" <darwi@linutronix.de>
Cc: Borislav Petkov <bp@alien8.de>, Ingo Molnar <mingo@redhat.com>,
Dave Hansen <dave.hansen@linux.intel.com>,
Thomas Gleixner <tglx@linutronix.de>,
John Ogness <john.ogness@linutronix.de>,
"H. Peter Anvin" <hpa@zytor.com>,
Andrew Cooper <andrew.cooper3@citrix.com>,
x86@kernel.org, x86-cpuid@lists.linux.dev,
LKML <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v1 10/40] x86/cpu: Remove leaf 0x2 parsing loop and add helpers
Date: Tue, 4 Mar 2025 10:26:03 +0100 [thread overview]
Message-ID: <Z8bHK391zKE4gUEW@gmail.com> (raw)
In-Reply-To: <20250304085152.51092-11-darwi@linutronix.de>
* Ahmed S. Darwish <darwi@linutronix.de> wrote:
> Leaf 0x2 output includes a "query count" byte where it was supposed to
> specify the number of repeated cpuid leaf 0x2 subleaf 0 queries needed
> to extract all of the hardware's cache and TLB descriptors.
s/cpuid
/CPUID
Please do this in the rest of the series too. (I did it for the first 9
patches.)
> +++ b/arch/x86/include/asm/cpuid/types.h
> @@ -0,0 +1,79 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +#ifndef _ASM_X86_CPUID_TYPES_H
> +#define _ASM_X86_CPUID_TYPES_H
> +
> +#include <linux/types.h>
> +
> +#include <asm/cpuid.h>
So that header organization is a bit messy: if <asm/cpuid.h> is
supposed to be the main header, why is there a <asm/cpuid/types.h>?
I'd suggest we follow the FPU header structure:
starship:~/tip/arch/x86/include/asm/fpu> ls -l
total 48
-rw-rw-r-- 1 mingo mingo 5732 Feb 27 19:24 api.h
-rw-rw-r-- 1 mingo mingo 671 Feb 26 16:13 regset.h
-rw-rw-r-- 1 mingo mingo 2203 Feb 27 13:52 sched.h
-rw-rw-r-- 1 mingo mingo 1110 Feb 27 19:24 signal.h
-rw-rw-r-- 1 mingo mingo 14741 Feb 27 19:24 types.h
-rw-rw-r-- 1 mingo mingo 811 Feb 26 16:13 xcr.h
-rw-rw-r-- 1 mingo mingo 4401 Feb 27 23:01 xstate.h
With <asm/cpuid/api.h> being the main header - established via a
separate preparatory patch.
This followup patch can then add <asm/cpuid/types.h> which will also be
included in <asm/cpuid/api.h>.
> +/*
> + * CPUID(0x2) parsing helpers
> + * Check for_each_leaf_0x2_desc() documentation.
> + */
> +
> +struct leaf_0x2_reg {
> + u32 : 31,
> + invalid : 1;
> +};
> +
> +union leaf_0x2_regs {
> + struct leaf_0x2_reg reg[4];
> + u32 regv[4];
> + u8 desc[16];
> +};
> +
> +/**
> + * get_leaf_0x2_regs() - Return sanitized leaf 0x2 register output
> + * @regs: Output parameter
> + *
> + * Get leaf 0x2 register output and store it in @regs. Invalid byte
> + * descriptors returned by the hardware will be force set to zero (the
> + * NULL cache/TLB descriptor) before returning them to the caller.
> + */
> +static inline void get_leaf_0x2_regs(union leaf_0x2_regs *regs)
Please prefix all new cpuid API functions and types with cpuid_.
> +#define for_each_leaf_0x2_desc(regs, desc) \
> + /* Skip the first byte as it is not a descriptor */ \
> + for (desc = &(regs).desc[1]; desc < &(regs).desc[16]; desc++)
The comment line can come before the macro.
> + get_leaf_0x2_regs(®s);
> + for_each_leaf_0x2_desc(regs, desc)
> + intel_tlb_lookup(*desc);
Nice interface otherwise.
Thanks,
Ingo
next prev parent reply other threads:[~2025-03-04 9:26 UTC|newest]
Thread overview: 57+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-04 8:51 [PATCH v1 00/40] x86: Leaf 0x2 and leaf 0x4 refactorings Ahmed S. Darwish
2025-03-04 8:51 ` [PATCH v1 01/40] x86/cacheinfo: Validate cpuid leaf 0x2 EDX output Ahmed S. Darwish
2025-03-04 8:51 ` [PATCH v1 02/40] x86/cpu: " Ahmed S. Darwish
2025-03-04 8:51 ` [PATCH v1 03/40] x86/cpu: Properly parse leaf 0x2 TLB descriptor 0x63 Ahmed S. Darwish
2025-03-04 8:51 ` [PATCH v1 04/40] x86/cpuid: Include linux/build_bug.h Ahmed S. Darwish
2025-03-04 8:51 ` [PATCH v1 05/40] x86/cpu: Remove unnecessary headers and reorder the rest Ahmed S. Darwish
2025-03-04 9:14 ` Ingo Molnar
2025-03-04 9:28 ` Ahmed S. Darwish
2025-03-04 8:51 ` [PATCH v1 06/40] x86/cpu: Use max() for leaf 0x2 TLB descriptors parsing Ahmed S. Darwish
2025-03-04 8:51 ` [PATCH v1 07/40] x86/cpu: Simplify TLB entry count storage Ahmed S. Darwish
2025-03-04 8:51 ` [PATCH v1 08/40] x86/cpu: Get rid of smp_store_cpu_info() indirection Ahmed S. Darwish
2025-03-04 8:51 ` [PATCH v1 09/40] x86/cpu: Remove unused TLB strings Ahmed S. Darwish
2025-03-04 8:51 ` [PATCH v1 10/40] x86/cpu: Remove leaf 0x2 parsing loop and add helpers Ahmed S. Darwish
2025-03-04 9:26 ` Ingo Molnar [this message]
2025-03-05 16:01 ` Ahmed S. Darwish
2025-03-04 8:51 ` [PATCH v1 11/40] x86/cacheinfo: Remove the P4 trace leftovers for real Ahmed S. Darwish
2025-03-04 8:51 ` [PATCH v1 12/40] x86/cacheinfo: Remove unnecessary headers and reorder the rest Ahmed S. Darwish
2025-03-04 8:51 ` [PATCH v1 13/40] x86/cacheinfo: Use cpuid leaf 0x2 parsing helpers Ahmed S. Darwish
2025-03-04 8:51 ` [PATCH v1 14/40] x86/cacheinfo: Refactor leaf 0x2 cache descriptor lookup Ahmed S. Darwish
2025-03-04 8:51 ` [PATCH v1 15/40] x86/cacheinfo: Properly name amd_cpuid4()'s first parameter Ahmed S. Darwish
2025-03-04 8:51 ` [PATCH v1 16/40] x86/cacheinfo: Use proper name for cacheinfo instances Ahmed S. Darwish
2025-03-04 8:51 ` [PATCH v1 17/40] x86/cacheinfo: Constify _cpuid4_info_regs instances Ahmed S. Darwish
2025-03-04 8:51 ` [PATCH v1 18/40] x86/cacheinfo: Align ci_info_init() assignment expressions Ahmed S. Darwish
2025-03-04 8:51 ` [PATCH v1 19/40] x86/cacheinfo: Standardize _cpuid4_info_regs instance naming Ahmed S. Darwish
2025-03-04 8:51 ` [PATCH v1 20/40] x86: treewide: Introduce x86_vendor_amd_or_hygon() Ahmed S. Darwish
2025-03-04 8:51 ` [PATCH v1 21/40] x86/cacheinfo: Consolidate AMD/Hygon leaf 0x8000001d calls Ahmed S. Darwish
2025-03-04 8:51 ` [PATCH v1 22/40] x86/cacheinfo: Separate amd_northbridge from _cpuid4_info_regs Ahmed S. Darwish
2025-03-04 8:51 ` [PATCH v1 23/40] x86/cacheinfo: Move AMD cache_disable_0/1 handling to separate file Ahmed S. Darwish
2025-03-04 8:51 ` [PATCH v1 24/40] x86/cacheinfo: Use sysfs_emit() for sysfs attributes show() Ahmed S. Darwish
2025-03-04 8:51 ` [PATCH v1 25/40] x86/cacheinfo: Separate Intel and AMD leaf 0x4 code paths Ahmed S. Darwish
2025-03-04 8:51 ` [PATCH v1 26/40] x86/cacheinfo: Rename _cpuid4_info_regs to _cpuid4_info Ahmed S. Darwish
2025-03-04 8:51 ` [PATCH v1 27/40] x86/cacheinfo: Clarify type markers for leaf 0x2 cache descriptors Ahmed S. Darwish
2025-03-04 8:51 ` [PATCH v1 28/40] x86/cacheinfo: Use enums for cache descriptor types Ahmed S. Darwish
2025-03-04 8:51 ` [PATCH v1 29/40] x86/cpu: Use enums for TLB " Ahmed S. Darwish
2025-03-04 8:51 ` [PATCH v1 30/40] sizes.h: Cover all possible x86 cpu cache sizes Ahmed S. Darwish
2025-03-04 9:35 ` Ingo Molnar
2025-03-05 16:18 ` Ahmed S. Darwish
2025-03-04 8:51 ` [PATCH v1 31/40] x86/cpu: Consolidate CPUID leaf 0x2 tables Ahmed S. Darwish
2025-03-04 8:51 ` [PATCH v1 32/40] x86/cacheinfo: Use consolidated leaf 0x2 descriptor table Ahmed S. Darwish
2025-03-04 8:51 ` [PATCH v1 33/40] x86/cpu: " Ahmed S. Darwish
2025-03-04 8:51 ` [PATCH v1 34/40] x86/cacheinfo: Separate leaf 0x2 handling and post-processing logic Ahmed S. Darwish
2025-03-04 8:51 ` [PATCH v1 35/40] x86/cacheinfo: Separate intel leaf 0x4 handling Ahmed S. Darwish
2025-03-04 8:51 ` [PATCH v1 36/40] x86/cacheinfo: Extract out cache level topology ID calculation Ahmed S. Darwish
2025-03-04 8:51 ` [PATCH v1 37/40] x86/cacheinfo: Extract out cache self-snoop checks Ahmed S. Darwish
2025-03-04 10:38 ` Andrew Cooper
2025-03-05 18:40 ` Ahmed S. Darwish
2025-03-05 18:42 ` Andrew Cooper
2025-03-05 18:58 ` Ahmed S. Darwish
2025-03-05 19:01 ` Andrew Cooper
2025-03-04 8:51 ` [PATCH v1 38/40] x86/cacheinfo: Relocate leaf 0x4 cache_type mapping Ahmed S. Darwish
2025-03-04 8:51 ` [PATCH v1 39/40] x86/cacheinfo: Introduce amd_hygon_cpu_has_l3_cache() Ahmed S. Darwish
2025-03-04 8:51 ` [PATCH v1 40/40] x86/cacheinfo: Apply maintainer-tip coding style fixes Ahmed S. Darwish
2025-03-04 9:19 ` [PATCH v1 00/40] x86: Leaf 0x2 and leaf 0x4 refactorings Ingo Molnar
2025-03-04 9:38 ` Ingo Molnar
2025-03-05 17:36 ` Ahmed S. Darwish
2025-03-04 9:33 ` Ingo Molnar
2025-03-05 16:38 ` Ahmed S. Darwish
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