From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2CCD41F4CAD; Tue, 4 Mar 2025 09:35:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741080949; cv=none; b=ASN8ZK8FeF+JnNosaddbM1OtIgl0zNljRRxaZWhj/saLHXxv4HnoPieytwU+XWdUqcO2J7b1amoMC5EvJOWlVEuWqRT7GsFEFAXfnly9vwnEHJsbb6IpSC6fF27fhV4GNJRDjDD60ecgbRtR89YtFvs5d70jQJA1MIsNB0j8rsM= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741080949; c=relaxed/simple; bh=OOxTMSOg7lRj8PaiKENPOz3rSc2lIXFyPelO8yUfKIY=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=AMvCUtx726T+Y0hKfUaExPYdf6TF+6s/yEGk6I9WAU9duStlJuuSoORjMJZ1n/RVHzM8c0n72sS5RFbQvpm0T8/DozQcqIXi6pQZoNtGWYCHyNYDfyv3pxujND18q6VJ9stbPqMT+dPVcce4CWiJF9pUbsDrCUTMmnOJGND0Uvs= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Kx/eSIfE; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Kx/eSIfE" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 29D46C4CEE5; Tue, 4 Mar 2025 09:35:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1741080948; bh=OOxTMSOg7lRj8PaiKENPOz3rSc2lIXFyPelO8yUfKIY=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=Kx/eSIfEYTqyJ0J8k+nF8/AEbXCGGF2GV0OgRGwjE6bFMz0IzMwoPLLUqXfkYkSxN MMUrBP4GuClisHs1i/tiOJG16n9DwkyUEzdC4VIRZ0AXMQgZhEaPaQBQ7LsYuD0T0A yXdleayg3eRqdb5eZo+GCvFM8e83W3XkAwgki5wz3jr4idNcjThBFcDejw8QUYCX0d WNsRqNiKFNlRPhY5jPFu8ucdXjfcIlEuUXyvAiQR32zr4qZuizqsn1+4S7kXigthfS 7X0yeRcXJMbsDwwpO0yM87YZZ6O9pkq5lOPiJ1vfOt3mfz1zmZDYjzG5bzJllzEQIS q5tQDkUx9ugyw== Date: Tue, 4 Mar 2025 10:35:43 +0100 From: Ingo Molnar To: "Ahmed S. Darwish" Cc: Borislav Petkov , Ingo Molnar , Dave Hansen , Thomas Gleixner , John Ogness , "H. Peter Anvin" , Andrew Cooper , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML Subject: Re: [PATCH v1 30/40] sizes.h: Cover all possible x86 cpu cache sizes Message-ID: References: <20250304085152.51092-1-darwi@linutronix.de> <20250304085152.51092-31-darwi@linutronix.de> Precedence: bulk X-Mailing-List: x86-cpuid@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250304085152.51092-31-darwi@linutronix.de> * Ahmed S. Darwish wrote: > Add size macros for 24/192/384 Kilobyes and 3/6/12/18/24 Megabytes. > > With that, the x86 subsystem can avoid locally defining its own macros > for CPU cache sizs. Please take some time to read your own changelogs: s/Kilobyes /Kilobytes s/sizs /sizes s/cpu /CPU Thanks, Ingo