From: Andrew Cooper <andrew.cooper3@citrix.com>
To: Jan Beulich <JBeulich@suse.com>,
xen-devel <xen-devel@lists.xenproject.org>
Subject: Re: [PATCH] x86/Intel: drop another 32-bit leftover
Date: Wed, 20 Dec 2017 19:25:53 +0000 [thread overview]
Message-ID: <013a2569-dbf5-4f14-6a20-f98604b313a8@citrix.com> (raw)
In-Reply-To: <5A282672020000780019523A@prv-mh.provo.novell.com>
On 06/12/17 16:18, Jan Beulich wrote:
> None of the models MISC_ENABLE MSR access is excluded for support 64-bit
> mode - drop the conditional from early_init_intel(). Also convert
> pointless rdmsr_safe() elsewhere to rdmsrl().
>
> Signed-off-by: Jan Beulich <jbeulich@suse.com>
Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
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prev parent reply other threads:[~2017-12-20 19:25 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-12-06 16:18 [PATCH] x86/Intel: drop another 32-bit leftover Jan Beulich
2017-12-20 19:25 ` Andrew Cooper [this message]
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