From: Boris Ostrovsky <boris.ostrovsky@oracle.com>
To: Meng Xu <mengxu@seas.upenn.edu>, Jan Beulich <JBeulich@suse.com>,
"xen-devel@lists.xenproject.org" <xen-devel@lists.xenproject.org>
Cc: xuquan8@huawei.com
Subject: Re: Question about the general performance counter overflow interrupt handling
Date: Fri, 31 Mar 2017 12:01:30 -0400 [thread overview]
Message-ID: <0eee0893-c3fc-c009-1e80-29a7dc939e01@oracle.com> (raw)
In-Reply-To: <CAENZ-+n+Z9hJEEtFgreApKO1B715APT-VZG63T-TZ8HN6HAAaA@mail.gmail.com>
>> When I program the general performance counter to trigger an overflow
>> interrupt, I set the following bits for the event selector register
>> and run a task to generate the L3 cache cache miss.
>> FLAG_ENABLE: 0x400000UL
>> FLAG_INT: 0x100000UL
>> FLAG_USR: 0x010000UL
>> L3_ALLMISS_EVENT 0x2E
>> L3_ALLMISS_MESI 0x41
>>
>> I'm sure the performance counter does overflow, but I didn't see any
>> interrupt was triggered. Maybe I missed something?
Did you program global registrers (MSR_CORE_PERF_GLOBAL_CTRL,
MSR_CORE_PERF_GLOBAL_OVF_CTRL)?
-boris
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next prev parent reply other threads:[~2017-03-31 16:01 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-03-31 15:41 Question about the general performance counter overflow interrupt handling Meng Xu
2017-03-31 15:46 ` Meng Xu
2017-03-31 16:01 ` Boris Ostrovsky [this message]
2017-03-31 17:32 ` Meng Xu
2017-03-31 17:49 ` Boris Ostrovsky
2017-03-31 15:52 ` Jan Beulich
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