From mboxrd@z Thu Jan 1 00:00:00 1970 From: Dario Faggioli Subject: [PATCHv2 2 of 2] Move IOMMU faults handling into softirq for AMD-Vi. Date: Thu, 05 Jan 2012 16:27:00 +0100 Message-ID: <1325777220.2728.11.camel@Solace> References: <1325776241.2728.5.camel@Solace> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============2544051390667607061==" Return-path: In-Reply-To: <1325776241.2728.5.camel@Solace> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xensource.com Errors-To: xen-devel-bounces@lists.xensource.com To: xen-devel@lists.xensource.com Cc: Wei Wang2 , Tim Deegan , "allen.m.kay@intel.com" , Jan Beulich List-Id: xen-devel@lists.xenproject.org --===============2544051390667607061== Content-Type: multipart/signed; micalg="pgp-sha1"; protocol="application/pgp-signature"; boundary="=-LgfSLpqc91p9nBEa/n3k" --=-LgfSLpqc91p9nBEa/n3k Content-Type: multipart/mixed; boundary="=-UGaeOSSswF4hJv9RKu01" --=-UGaeOSSswF4hJv9RKu01 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Dealing with interrupts from AMD-Vi IOMMU(s) is deferred to a softirq-taskl= et, raised by the actual IRQ handler. To avoid more interrupts being generated (because of further faults), they must be masked in the IOMMU within the lo= w level IRQ handler and enabled back in the tasklet body. Notice that this ma= y cause the log to overflow, but none of the existing entry will be overwritt= en. Signed-off-by: Dario Faggioli diff -r 3cb587bb34d0 xen/drivers/passthrough/amd/iommu_init.c --- a/xen/drivers/passthrough/amd/iommu_init.c Thu Jan 05 15:12:35 2012 +01= 00 +++ b/xen/drivers/passthrough/amd/iommu_init.c Thu Jan 05 15:14:03 2012 +01= 00 @@ -32,6 +32,8 @@ =20 static int __initdata nr_amd_iommus; =20 +static struct tasklet amd_iommu_fault_tasklet; + unsigned short ivrs_bdf_entries; static struct radix_tree_root ivrs_maps; struct list_head amd_iommu_head; @@ -522,12 +524,10 @@ static void parse_event_log_entry(struct } } =20 -static void amd_iommu_page_fault(int irq, void *dev_id, - struct cpu_user_regs *regs) +static void __do_amd_iommu_page_fault(struct amd_iommu *iommu) { u32 entry; unsigned long flags; - struct amd_iommu *iommu =3D dev_id; =20 spin_lock_irqsave(&iommu->lock, flags); amd_iommu_read_event_log(iommu); @@ -546,6 +546,45 @@ static void amd_iommu_page_fault(int irq spin_unlock_irqrestore(&iommu->lock, flags); } =20 +static void do_amd_iommu_page_fault(unsigned long data) +{ + struct amd_iommu *iommu; + + if ( !iommu_found() ) + { + AMD_IOMMU_DEBUG("no device found, something must be very wrong!\n"= ); + return; + } + + /* + * No matter from whom the interrupt came from, check all the + * IOMMUs present in the system. This allows for having just one + * tasklet (instead of one per each IOMMUs) and should be more than + * fine, considering how rare the event of a fault should be. + */ + for_each_amd_iommu ( iommu ) + __do_amd_iommu_page_fault(iommu); +} + +static void amd_iommu_page_fault(int irq, void *dev_id, + struct cpu_user_regs *regs) +{ + u32 entry; + unsigned long flags; + struct amd_iommu *iommu =3D dev_id; + + /* silence interrupts. The tasklet will enable them back */ + spin_lock_irqsave(&iommu->lock, flags); + entry =3D readl(iommu->mmio_base + IOMMU_STATUS_MMIO_OFFSET); + iommu_clear_bit(&entry, IOMMU_STATUS_EVENT_LOG_INT_SHIFT); + writel(entry, iommu->mmio_base+IOMMU_STATUS_MMIO_OFFSET); + spin_unlock_irqrestore(&iommu->lock, flags); + + /* Flag the tasklet as runnable so that it can execute, clear + * the log and re-enable interrupts. */ + tasklet_schedule(&amd_iommu_fault_tasklet); +} + static int __init set_iommu_interrupt_handler(struct amd_iommu *iommu) { int irq, ret; @@ -884,6 +923,8 @@ int __init amd_iommu_init(void) if ( amd_iommu_init_one(iommu) !=3D 0 ) goto error_out; =20 + softirq_tasklet_init(&amd_iommu_fault_tasklet, do_amd_iommu_page_fault= , 0); + return 0; =20 error_out: --=20 <> (Raistlin Majere) ------------------------------------------------------------------- Dario Faggioli, http://retis.sssup.it/people/faggioli Senior Software Engineer, Citrix Systems R&D Ltd., Cambridge (UK) PhD Candidate, ReTiS Lab, Scuola Superiore Sant'Anna, Pisa (Italy) --=-UGaeOSSswF4hJv9RKu01 Content-Disposition: attachment; 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