From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jean Guyader Subject: [PATCH 2/2] intel gpu passthrough: Expose vendor specific pci cap on host bridge. Date: Tue, 17 Jan 2012 16:40:25 +0000 Message-ID: <1326818425-26194-2-git-send-email-jean.guyader@eu.citrix.com> References: <1326818425-26194-1-git-send-email-jean.guyader@eu.citrix.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="------------true" Return-path: In-Reply-To: <1326818425-26194-1-git-send-email-jean.guyader@eu.citrix.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xensource.com Errors-To: xen-devel-bounces@lists.xensource.com To: xen-devel@lists.xensource.com Cc: Ian.Jackson@eu.citrix.com, djmagee@mageenet.net, allen.m.kay@intel.com, Jean Guyader , Ross.Philipson@citrix.com List-Id: xen-devel@lists.xenproject.org --------------true Content-Type: text/plain; charset="UTF-8"; format=fixed Content-Transfer-Encoding: 8bit Some versions of the Windows Intel GPU driver expect the vendor PCI capability to be there on the host bridge config space when passing through a Intel GPU. Signed-off-by: Jean Guyader --- hw/pt-graphics.c | 59 +++++++++++++++++++++++++++++++++++++++++++++++++---- 1 files changed, 54 insertions(+), 5 deletions(-) --------------true Content-Type: text/x-patch; name="0002-intel-gpu-passthrough-Expose-vendor-specific-pci-cap.patch" Content-Transfer-Encoding: 8bit Content-Disposition: attachment; filename="0002-intel-gpu-passthrough-Expose-vendor-specific-pci-cap.patch" diff --git a/hw/pt-graphics.c b/hw/pt-graphics.c index fec7390..55cbf75 100644 --- a/hw/pt-graphics.c +++ b/hw/pt-graphics.c @@ -60,6 +60,53 @@ void igd_pci_write(PCIDevice *pci_dev, uint32_t config_addr, uint32_t val, int l } } +#define PCI_INTEL_VENDOR_CAP 0x34 +#define PCI_INTEL_VENDOR_CAP_TYPE 0x09 +/* + * This function returns 0 is the value hasn't been + * updated. That mean the offset doesn't anything to + * do with the vendor capability. + */ +static uint32_t igd_pci_read_vendor_cap(PCIDevice *pci_dev, uint32_t config_addr, int len, + uint32_t *val) +{ + struct pci_dev *pci_dev_host_bridge = pt_pci_get_dev(0, 0, 0); + uint32_t vendor_cap = 0; + uint32_t cap_type = 0; + uint32_t cap_size = 0; + + vendor_cap = pt_pci_host_read(pci_dev_host_bridge, PCI_INTEL_VENDOR_CAP, 1); + if (!vendor_cap) + return 0; + + cap_type = pt_pci_host_read(pci_dev_host_bridge, vendor_cap, 1); + if (cap_type != PCI_INTEL_VENDOR_CAP_TYPE) + return 0; + + if (config_addr == PCI_INTEL_VENDOR_CAP) + { + *val = vendor_cap; + return 1; + } + + /* Remove the next capability link */ + if (config_addr == vendor_cap + 1) + { + *val = 0; + return 1; + } + + cap_size = pt_pci_host_read(pci_dev_host_bridge, vendor_cap + 2, 1); + if (config_addr >= vendor_cap && + config_addr + len < vendor_cap + cap_size) + { + *val = pt_pci_host_read(pci_dev_host_bridge, config_addr, len); + return 1; + } + + return 0; +} + uint32_t igd_pci_read(PCIDevice *pci_dev, uint32_t config_addr, int len) { struct pci_dev *pci_dev_host_bridge = pt_pci_get_dev(0, 0, 0); @@ -82,14 +129,16 @@ uint32_t igd_pci_read(PCIDevice *pci_dev, uint32_t config_addr, int len) case 0xa4: /* SNB: graphics base of stolen memory */ case 0xa8: /* SNB: base of GTT stolen memory */ val = pt_pci_host_read(pci_dev_host_bridge, config_addr, len); -#ifdef PT_DEBUG_PCI_CONFIG_ACCESS - PT_LOG_DEV(pci_dev, "addr=%x len=%x val=%x\n", - config_addr, len, val); -#endif break; default: - val = pci_default_read_config(pci_dev, config_addr, len); + if (!igd_pci_read_vendor_cap(pci_dev, config_addr, len, &val)) + val = pci_default_read_config(pci_dev, config_addr, len); + } +#ifdef PT_DEBUG_PCI_CONFIG_ACCESS + PT_LOG_DEV(pci_dev, "addr=%x len=%x val=%x\n", + config_addr, len, val); +#endif return val; } --------------true Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel --------------true--