[PATCH 4/7] xen/arm: set the SMP bit in the ACTLR register

[Stefano Stabellini <stefano.stabellini@eu.citrix.com>]

>From the Cortex A15 manual:

"Enables the processor to receive instruction cache, BTB, and TLB maintenance
operations from other processors"

...

"You must set this bit before enabling the caches and MMU, or
performing any cache and TLB maintenance operations. The only time
you must clear this bit is during a processor power-down sequence"


Changes in v2:
- detect the processor ID and call a processor specific initialization
function;
- move the ACTLR initialization to the CortexA15 initialization
function;
- move the ACTLR_* defines to processor-ca15.h.


Signed-off-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
Acked-by: Tim Deegan <tim@xen.org>
---
 xen/arch/arm/Makefile                |    1 +
 xen/arch/arm/head.S                  |   10 +++++++
 xen/arch/arm/proc-ca15.S             |   28 +++++++++++++++++++++
 xen/include/asm-arm/cpregs.h         |    1 +
 xen/include/asm-arm/processor-ca15.h |   45 ++++++++++++++++++++++++++++++++++
 xen/include/asm-arm/processor.h      |    3 ++
 6 files changed, 88 insertions(+), 0 deletions(-)
 create mode 100644 xen/arch/arm/proc-ca15.S
 create mode 100644 xen/include/asm-arm/processor-ca15.h

diff --git a/xen/arch/arm/Makefile b/xen/arch/arm/Makefile
index 634b620..d3e34bc 100644
--- a/xen/arch/arm/Makefile
+++ b/xen/arch/arm/Makefile
@@ -13,6 +13,7 @@ obj-y += irq.o
 obj-y += kernel.o
 obj-y += mm.o
 obj-y += mode_switch.o
+obj-y += proc-ca15.o
 obj-y += p2m.o
 obj-y += percpu.o
 obj-y += guestcopy.o
diff --git a/xen/arch/arm/head.S b/xen/arch/arm/head.S
index 4506244..25993d6 100644
--- a/xen/arch/arm/head.S
+++ b/xen/arch/arm/head.S
@@ -19,6 +19,7 @@
 
 #include <asm/config.h>
 #include <asm/page.h>
+#include <asm/processor-ca15.h>
 #include <asm/asm_defns.h>
 
 #define PT_PT  0xe7f /* nG=1, AF=1, SH=10, AP=01, NS=1, ATTR=111, T=1, P=1 */
@@ -148,6 +149,15 @@ skip_bss:
 
 	PRINT("- Setting up control registers -\r\n")
 	
+	/* Read CPU ID */
+	mrc   CP32(r0, MIDR)
+	ldr   r1, =(MIDR_MASK)
+	and   r0, r0, r1
+	/* Is this a Cortex A15? */
+	ldr   r1, =(CORTEX_A15_ID)
+	teq   r0, r1
+	bleq  cortex_a15_init
+
 	/* Set up memory attribute type tables */
 	ldr   r0, =MAIR0VAL
 	ldr   r1, =MAIR1VAL
diff --git a/xen/arch/arm/proc-ca15.S b/xen/arch/arm/proc-ca15.S
new file mode 100644
index 0000000..5a5bf64
--- /dev/null
+++ b/xen/arch/arm/proc-ca15.S
@@ -0,0 +1,28 @@
+/*
+ * xen/arch/arm/proc-ca15.S
+ *
+ * Cortex A15 specific initializations
+ *
+ * Copyright (c) 2011 Citrix Systems.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <asm/asm_defns.h>
+#include <asm/processor-ca15.h>
+
+.globl cortex_a15_init
+cortex_a15_init:
+	/* Set up the SMP bit in ACTLR */
+	mrc   CP32(r0, ACTLR)
+	orr   r0, r0, #(ACTLR_CA15_SMP) /* enable SMP bit*/
+	mcr   CP32(r0, ACTLR)
+	mov   pc, lr
diff --git a/xen/include/asm-arm/cpregs.h b/xen/include/asm-arm/cpregs.h
index 34a9e93..3b51845 100644
--- a/xen/include/asm-arm/cpregs.h
+++ b/xen/include/asm-arm/cpregs.h
@@ -104,6 +104,7 @@
 /* Coprocessor 15 */
 
 /* CP15 CR0: CPUID and Cache Type Registers */
+#define MIDR            p15,0,c0,c0,0   /* Main ID Register */
 #define MPIDR           p15,0,c0,c0,5   /* Multiprocessor Affinity Register */
 #define ID_PFR0         p15,0,c0,c1,0   /* Processor Feature Register 0 */
 #define ID_PFR1         p15,0,c0,c1,1   /* Processor Feature Register 1 */
diff --git a/xen/include/asm-arm/processor-ca15.h b/xen/include/asm-arm/processor-ca15.h
new file mode 100644
index 0000000..86231b3
--- /dev/null
+++ b/xen/include/asm-arm/processor-ca15.h
@@ -0,0 +1,45 @@
+#ifndef __ASM_ARM_PROCESSOR_CA15_H
+#define __ASM_ARM_PROCESSOR_CA15_H
+
+
+#define CORTEX_A15_ID     (0x410FC0F0)
+
+/* ACTLR Auxiliary Control Register, Cortex A15 */
+#define ACTLR_CA15_SNOOP_DELAYED      (1<<31)
+#define ACTLR_CA15_MAIN_CLOCK         (1<<30)
+#define ACTLR_CA15_NEON_CLOCK         (1<<29)
+#define ACTLR_CA15_NONCACHE           (1<<24)
+#define ACTLR_CA15_INORDER_REQ        (1<<23)
+#define ACTLR_CA15_INORDER_LOAD       (1<<22)
+#define ACTLR_CA15_L2_TLB_PREFETCH    (1<<21)
+#define ACTLR_CA15_L2_IPA_PA_CACHE    (1<<20)
+#define ACTLR_CA15_L2_CACHE           (1<<19)
+#define ACTLR_CA15_L2_PA_CACHE        (1<<18)
+#define ACTLR_CA15_TLB                (1<<17)
+#define ACTLR_CA15_STRONGY_ORDERED    (1<<16)
+#define ACTLR_CA15_INORDER            (1<<15)
+#define ACTLR_CA15_FORCE_LIM          (1<<14)
+#define ACTLR_CA15_CP_FLUSH           (1<<13)
+#define ACTLR_CA15_CP_PUSH            (1<<12)
+#define ACTLR_CA15_LIM                (1<<11)
+#define ACTLR_CA15_SER                (1<<10)
+#define ACTLR_CA15_OPT                (1<<9)
+#define ACTLR_CA15_WFI                (1<<8)
+#define ACTLR_CA15_WFE                (1<<7)
+#define ACTLR_CA15_SMP                (1<<6)
+#define ACTLR_CA15_PLD                (1<<5)
+#define ACTLR_CA15_IP                 (1<<4)
+#define ACTLR_CA15_MICRO_BTB          (1<<3)
+#define ACTLR_CA15_LOOP_ONE           (1<<2)
+#define ACTLR_CA15_LOOP_DISABLE       (1<<1)
+#define ACTLR_CA15_BTB                (1<<0)
+
+#endif /* __ASM_ARM_PROCESSOR_CA15_H */
+/*
+ * Local variables:
+ * mode: C
+ * c-set-style: "BSD"
+ * c-basic-offset: 4
+ * indent-tabs-mode: nil
+ * End:
+ */
diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h
index 3849b23..e0c0beb 100644
--- a/xen/include/asm-arm/processor.h
+++ b/xen/include/asm-arm/processor.h
@@ -3,6 +3,9 @@
 
 #include <asm/cpregs.h>
 
+/* MIDR Main ID Register */
+#define MIDR_MASK    0xff0ffff0
+
 /* TTBCR Translation Table Base Control Register */
 #define TTBCR_EAE    0x80000000
 #define TTBCR_N_MASK 0x07
-- 
1.7.2.5