[PATCH 0/9] nested vmx: expose some vmx features to L1 VMM

[PATCH 0/9] nested vmx: expose some vmx features to L1 VMM

[Dongxiao Xu]

This patch series expose some vmx features to L1 VMM, including MTF, NMI-window exiting, etc.
Please help to review and pull.

Thanks,
Dongxiao

Dongxiao Xu (9):
  nested vmx: enable Monitor Trap Flag for L1 VMM
  nested vmx: enable NMI-window exiting for L1 VMM
  nested vmx: enable secondary processor-based VM-Execution controls
  nested vmx: enable Descriptor-table exiting for L1 VMM
  nested vmx: enable VMX-preemption timer for L1 VMM
  nested vmx: enable save VMX-preemption timer feature for L1 VMM
  nested vmx: enable load and save IA32_PAT feature for L1 VMM
  nested vmx: enable load and save IA32_EFER feature for L1 VMM
  nested vmx: enable load IA32_PERF_GLOBAL_CTRL feature for L1 VMM

 xen/arch/x86/hvm/vmx/vmx.c         |    2 +-
 xen/arch/x86/hvm/vmx/vvmx.c        |  108 +++++++++++++++++++++++++++++++-----
 xen/include/asm-x86/hvm/vmx/vmcs.h |   12 ++++
 xen/include/asm-x86/hvm/vmx/vmx.h  |    1 +
 4 files changed, 108 insertions(+), 15 deletions(-)

[PATCH 1/9] nested vmx: enable Monitor Trap Flag for L1 VMM

[Dongxiao Xu]

Signed-off-by: Dongxiao Xu <dongxiao.xu@intel.com>
---
 xen/arch/x86/hvm/vmx/vvmx.c |   10 ++++++++--
 1 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/xen/arch/x86/hvm/vmx/vvmx.c b/xen/arch/x86/hvm/vmx/vvmx.c
index 4f6c712..c953278 100644
--- a/xen/arch/x86/hvm/vmx/vvmx.c
+++ b/xen/arch/x86/hvm/vmx/vvmx.c
@@ -1259,7 +1259,7 @@ int nvmx_msr_read_intercept(unsigned int msr, u64 *msr_content)
         break;
     case MSR_IA32_VMX_PROCBASED_CTLS:
         /* 1-seetings */
-        data = (CPU_BASED_HLT_EXITING |
+        data = CPU_BASED_HLT_EXITING |
                CPU_BASED_VIRTUAL_INTR_PENDING |
                CPU_BASED_CR8_LOAD_EXITING |
                CPU_BASED_CR8_STORE_EXITING |
@@ -1272,7 +1272,8 @@ int nvmx_msr_read_intercept(unsigned int msr, u64 *msr_content)
                CPU_BASED_ACTIVATE_IO_BITMAP |
                CPU_BASED_USE_TSC_OFFSETING |
                CPU_BASED_UNCOND_IO_EXITING |
-               CPU_BASED_RDTSC_EXITING);
+               CPU_BASED_RDTSC_EXITING |
+               CPU_BASED_MONITOR_TRAP_FLAG;
         /* bit 1, 4-6,8,13-16,26 must be 1 (refer G4 of SDM) */
         tmp = ( (1<<26) | (0xf << 13) | 0x100 | (0x7 << 4) | 0x2);
         /* 0-settings */
@@ -1475,6 +1476,11 @@ int nvmx_n2_vmexit_handler(struct cpu_user_regs *regs,
         if ( ctrl & CPU_BASED_VIRTUAL_NMI_PENDING )
             nvcpu->nv_vmexit_pending = 1;
         break;
+    case EXIT_REASON_MONITOR_TRAP_FLAG:
+        ctrl = __n2_exec_control(v);
+        if ( ctrl & CPU_BASED_MONITOR_TRAP_FLAG)
+            nvcpu->nv_vmexit_pending = 1;
+        break;
     /* L1 has priority handling several other types of exits */
     case EXIT_REASON_HLT:
         ctrl = __n2_exec_control(v);
-- 
1.7.1

[PATCH 2/9] nested vmx: enable NMI-window exiting for L1 VMM

[Dongxiao Xu]

Signed-off-by: Dongxiao Xu <dongxiao.xu@intel.com>
---
 xen/arch/x86/hvm/vmx/vvmx.c |    3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)

diff --git a/xen/arch/x86/hvm/vmx/vvmx.c b/xen/arch/x86/hvm/vmx/vvmx.c
index c953278..8f75bf4 100644
--- a/xen/arch/x86/hvm/vmx/vvmx.c
+++ b/xen/arch/x86/hvm/vmx/vvmx.c
@@ -1273,7 +1273,8 @@ int nvmx_msr_read_intercept(unsigned int msr, u64 *msr_content)
                CPU_BASED_USE_TSC_OFFSETING |
                CPU_BASED_UNCOND_IO_EXITING |
                CPU_BASED_RDTSC_EXITING |
-               CPU_BASED_MONITOR_TRAP_FLAG;
+               CPU_BASED_MONITOR_TRAP_FLAG |
+               CPU_BASED_VIRTUAL_NMI_PENDING;
         /* bit 1, 4-6,8,13-16,26 must be 1 (refer G4 of SDM) */
         tmp = ( (1<<26) | (0xf << 13) | 0x100 | (0x7 << 4) | 0x2);
         /* 0-settings */
-- 
1.7.1

[PATCH 3/9] nested vmx: enable secondary processor-based VM-Execution controls

[Dongxiao Xu]

Enable secondary processor-based control in VMCS

Besides that, add a helper function to get the certain control bit
in secondary processor-based control MSR.

Signed-off-by: Dongxiao Xu <dongxiao.xu@intel.com>
Signed-off-by: Xiantao Zhang <xiantao.zhang@intel.com>
---
 xen/arch/x86/hvm/vmx/vmx.c        |    2 +-
 xen/arch/x86/hvm/vmx/vvmx.c       |   31 ++++++++++++++++++++++++++++---
 xen/include/asm-x86/hvm/vmx/vmx.h |    1 +
 3 files changed, 30 insertions(+), 4 deletions(-)

diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c
index 00ca124..3bb0d99 100644
--- a/xen/arch/x86/hvm/vmx/vmx.c
+++ b/xen/arch/x86/hvm/vmx/vmx.c
@@ -344,7 +344,7 @@ void vmx_update_cpu_exec_control(struct vcpu *v)
         __vmwrite(CPU_BASED_VM_EXEC_CONTROL, v->arch.hvm_vmx.exec_control);
 }
 
-static void vmx_update_secondary_exec_control(struct vcpu *v)
+void vmx_update_secondary_exec_control(struct vcpu *v)
 {
     if ( nestedhvm_vcpu_in_guestmode(v) )
         nvmx_update_secondary_exec_control(v,
diff --git a/xen/arch/x86/hvm/vmx/vvmx.c b/xen/arch/x86/hvm/vmx/vvmx.c
index 8f75bf4..14a3d62 100644
--- a/xen/arch/x86/hvm/vmx/vvmx.c
+++ b/xen/arch/x86/hvm/vmx/vvmx.c
@@ -244,6 +244,17 @@ static inline u32 __n2_exec_control(struct vcpu *v)
     return __get_vvmcs(nvcpu->nv_vvmcx, CPU_BASED_VM_EXEC_CONTROL);
 }
 
+static inline u32 __n2_secondary_exec_control(struct vcpu *v)
+{
+    struct nestedvcpu *nvcpu = &vcpu_nestedhvm(v);
+    u64 second_ctrl = 0;
+
+    if ( __n2_exec_control(v) & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS )
+        second_ctrl = __get_vvmcs(nvcpu->nv_vvmcx, SECONDARY_VM_EXEC_CONTROL);
+
+    return second_ctrl;
+}
+
 static int vmx_inst_check_privilege(struct cpu_user_regs *regs, int vmxop_check)
 {
     struct vcpu *v = current;
@@ -454,7 +465,6 @@ void nvmx_update_exec_control(struct vcpu *v, u32 host_cntrl)
     /* Enforce the removed features */
     shadow_cntrl &= ~(CPU_BASED_TPR_SHADOW
                       | CPU_BASED_ACTIVATE_MSR_BITMAP
-                      | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
                       | CPU_BASED_ACTIVATE_IO_BITMAP
                       | CPU_BASED_UNCOND_IO_EXITING);
     shadow_cntrl |= host_cntrl;
@@ -487,7 +497,12 @@ void nvmx_update_exec_control(struct vcpu *v, u32 host_cntrl)
 void nvmx_update_secondary_exec_control(struct vcpu *v,
                                             unsigned long value)
 {
-    set_shadow_control(v, SECONDARY_VM_EXEC_CONTROL, value);
+    u32 shadow_cntrl;
+    struct nestedvcpu *nvcpu = &vcpu_nestedhvm(v);
+
+    shadow_cntrl = __get_vvmcs(nvcpu->nv_vvmcx, SECONDARY_VM_EXEC_CONTROL);
+    shadow_cntrl |= value;
+    set_shadow_control(v, SECONDARY_VM_EXEC_CONTROL, shadow_cntrl);
 }
 
 static void nvmx_update_pin_control(struct vcpu *v, unsigned long host_cntrl)
@@ -714,6 +729,7 @@ static void load_shadow_control(struct vcpu *v)
      */
     nvmx_update_pin_control(v, vmx_pin_based_exec_control);
     vmx_update_cpu_exec_control(v);
+    vmx_update_secondary_exec_control(v);
     nvmx_update_exit_control(v, vmx_vmexit_control);
     nvmx_update_entry_control(v);
     vmx_update_exception_bitmap(v);
@@ -923,6 +939,7 @@ static void virtual_vmexit(struct cpu_user_regs *regs)
         v->arch.hvm_vcpu.guest_efer &= ~(EFER_LMA | EFER_LME);
 
     vmx_update_cpu_exec_control(v);
+    vmx_update_secondary_exec_control(v);
     vmx_update_exception_bitmap(v);
 
     load_vvmcs_host_state(v);
@@ -1274,12 +1291,20 @@ int nvmx_msr_read_intercept(unsigned int msr, u64 *msr_content)
                CPU_BASED_UNCOND_IO_EXITING |
                CPU_BASED_RDTSC_EXITING |
                CPU_BASED_MONITOR_TRAP_FLAG |
-               CPU_BASED_VIRTUAL_NMI_PENDING;
+               CPU_BASED_VIRTUAL_NMI_PENDING |
+               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
         /* bit 1, 4-6,8,13-16,26 must be 1 (refer G4 of SDM) */
         tmp = ( (1<<26) | (0xf << 13) | 0x100 | (0x7 << 4) | 0x2);
         /* 0-settings */
         data = ((data | tmp) << 32) | (tmp);
         break;
+    case MSR_IA32_VMX_PROCBASED_CTLS2:
+        /* 1-seetings */
+        data = 0;
+        /* 0-settings */
+        tmp = 0;
+        data = (data << 32) | tmp;
+        break;
     case MSR_IA32_VMX_EXIT_CTLS:
         /* 1-seetings */
         /* bit 0-8, 10,11,13,14,16,17 must be 1 (refer G4 of SDM) */
diff --git a/xen/include/asm-x86/hvm/vmx/vmx.h b/xen/include/asm-x86/hvm/vmx/vmx.h
index edde077..c4c2fe8 100644
--- a/xen/include/asm-x86/hvm/vmx/vmx.h
+++ b/xen/include/asm-x86/hvm/vmx/vmx.h
@@ -70,6 +70,7 @@ void vmx_realmode(struct cpu_user_regs *regs);
 void vmx_update_debug_state(struct vcpu *v);
 void vmx_update_exception_bitmap(struct vcpu *v);
 void vmx_update_cpu_exec_control(struct vcpu *v);
+void vmx_update_secondary_exec_control(struct vcpu *v);
 
 
 /*
-- 
1.7.1

[PATCH 4/9] nested vmx: enable Descriptor-table exiting for L1 VMM

[Dongxiao Xu]

Signed-off-by: Dongxiao Xu <dongxiao.xu@intel.com>
---
 xen/arch/x86/hvm/vmx/vvmx.c        |    8 +++++++-
 xen/include/asm-x86/hvm/vmx/vmcs.h |    1 +
 2 files changed, 8 insertions(+), 1 deletions(-)

diff --git a/xen/arch/x86/hvm/vmx/vvmx.c b/xen/arch/x86/hvm/vmx/vvmx.c
index 14a3d62..23c949b 100644
--- a/xen/arch/x86/hvm/vmx/vvmx.c
+++ b/xen/arch/x86/hvm/vmx/vvmx.c
@@ -1300,7 +1300,7 @@ int nvmx_msr_read_intercept(unsigned int msr, u64 *msr_content)
         break;
     case MSR_IA32_VMX_PROCBASED_CTLS2:
         /* 1-seetings */
-        data = 0;
+        data = SECONDARY_EXEC_DESCRIPTOR_TABLE_EXITING;
         /* 0-settings */
         tmp = 0;
         data = (data << 32) | tmp;
@@ -1507,6 +1507,12 @@ int nvmx_n2_vmexit_handler(struct cpu_user_regs *regs,
         if ( ctrl & CPU_BASED_MONITOR_TRAP_FLAG)
             nvcpu->nv_vmexit_pending = 1;
         break;
+    case EXIT_REASON_ACCESS_GDTR_OR_IDTR:
+    case EXIT_REASON_ACCESS_LDTR_OR_TR:
+        ctrl = __n2_secondary_exec_control(v);
+        if ( ctrl & SECONDARY_EXEC_DESCRIPTOR_TABLE_EXITING )
+            nvcpu->nv_vmexit_pending = 1;
+        break;
     /* L1 has priority handling several other types of exits */
     case EXIT_REASON_HLT:
         ctrl = __n2_exec_control(v);
diff --git a/xen/include/asm-x86/hvm/vmx/vmcs.h b/xen/include/asm-x86/hvm/vmx/vmcs.h
index 4f58991..053de17 100644
--- a/xen/include/asm-x86/hvm/vmx/vmcs.h
+++ b/xen/include/asm-x86/hvm/vmx/vmcs.h
@@ -179,6 +179,7 @@ extern u32 vmx_vmentry_control;
 
 #define SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x00000001
 #define SECONDARY_EXEC_ENABLE_EPT               0x00000002
+#define SECONDARY_EXEC_DESCRIPTOR_TABLE_EXITING 0x00000004
 #define SECONDARY_EXEC_ENABLE_RDTSCP            0x00000008
 #define SECONDARY_EXEC_ENABLE_VPID              0x00000020
 #define SECONDARY_EXEC_WBINVD_EXITING           0x00000040
-- 
1.7.1

[PATCH 5/9] nested vmx: enable VMX-preemption timer for L1 VMM

[Dongxiao Xu]

Signed-off-by: Dongxiao Xu <dongxiao.xu@intel.com>
---
 xen/arch/x86/hvm/vmx/vvmx.c        |   18 ++++++++++++++++--
 xen/include/asm-x86/hvm/vmx/vmcs.h |    1 +
 2 files changed, 17 insertions(+), 2 deletions(-)

diff --git a/xen/arch/x86/hvm/vmx/vvmx.c b/xen/arch/x86/hvm/vmx/vvmx.c
index 23c949b..e5d812a 100644
--- a/xen/arch/x86/hvm/vmx/vvmx.c
+++ b/xen/arch/x86/hvm/vmx/vvmx.c
@@ -237,6 +237,13 @@ static void reg_write(struct cpu_user_regs *regs,
     *pval = value;
 }
 
+static inline u32 __n2_pin_exec_control(struct vcpu *v)
+{
+    struct nestedvcpu *nvcpu = &vcpu_nestedhvm(v);
+
+    return __get_vvmcs(nvcpu->nv_vvmcx, PIN_BASED_VM_EXEC_CONTROL);
+}
+
 static inline u32 __n2_exec_control(struct vcpu *v)
 {
     struct nestedvcpu *nvcpu = &vcpu_nestedhvm(v);
@@ -511,7 +518,6 @@ static void nvmx_update_pin_control(struct vcpu *v, unsigned long host_cntrl)
     struct nestedvcpu *nvcpu = &vcpu_nestedhvm(v);
 
     shadow_cntrl = __get_vvmcs(nvcpu->nv_vvmcx, PIN_BASED_VM_EXEC_CONTROL);
-    shadow_cntrl &= ~PIN_BASED_PREEMPT_TIMER;
     shadow_cntrl |= host_cntrl;
     __vmwrite(PIN_BASED_VM_EXEC_CONTROL, shadow_cntrl);
 }
@@ -641,6 +647,7 @@ static const u16 vmcs_gstate_field[] = {
     GUEST_INTERRUPTIBILITY_INFO,
     GUEST_ACTIVITY_STATE,
     GUEST_SYSENTER_CS,
+    GUEST_PREEMPTION_TIMER,
     /* natural */
     GUEST_ES_BASE,
     GUEST_CS_BASE,
@@ -1269,7 +1276,9 @@ int nvmx_msr_read_intercept(unsigned int msr, u64 *msr_content)
         break;
     case MSR_IA32_VMX_PINBASED_CTLS:
         /* 1-seetings */
-        data = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
+        data = PIN_BASED_EXT_INTR_MASK |
+               PIN_BASED_NMI_EXITING |
+               PIN_BASED_PREEMPT_TIMER;
         data <<= 32;
 	/* 0-settings */
         data |= 0;
@@ -1513,6 +1522,11 @@ int nvmx_n2_vmexit_handler(struct cpu_user_regs *regs,
         if ( ctrl & SECONDARY_EXEC_DESCRIPTOR_TABLE_EXITING )
             nvcpu->nv_vmexit_pending = 1;
         break;
+    case EXIT_REASON_VMX_PREEMPTION_TIMER_EXPIRED:
+        ctrl = __n2_pin_exec_control(v);
+        if ( ctrl & PIN_BASED_PREEMPT_TIMER )
+            nvcpu->nv_vmexit_pending = 1;
+        break;
     /* L1 has priority handling several other types of exits */
     case EXIT_REASON_HLT:
         ctrl = __n2_exec_control(v);
diff --git a/xen/include/asm-x86/hvm/vmx/vmcs.h b/xen/include/asm-x86/hvm/vmx/vmcs.h
index 053de17..fbe9a52 100644
--- a/xen/include/asm-x86/hvm/vmx/vmcs.h
+++ b/xen/include/asm-x86/hvm/vmx/vmcs.h
@@ -357,6 +357,7 @@ enum vmcs_field {
     GUEST_INTERRUPTIBILITY_INFO     = 0x00004824,
     GUEST_ACTIVITY_STATE            = 0x00004826,
     GUEST_SYSENTER_CS               = 0x0000482A,
+    GUEST_PREEMPTION_TIMER          = 0x0000482e,
     HOST_SYSENTER_CS                = 0x00004c00,
     CR0_GUEST_HOST_MASK             = 0x00006000,
     CR4_GUEST_HOST_MASK             = 0x00006002,
-- 
1.7.1

[PATCH 6/9] nested vmx: enable save VMX-preemption timer feature for L1 VMM

[Dongxiao Xu]

Signed-off-by: Dongxiao Xu <dongxiao.xu@intel.com>
---
 xen/arch/x86/hvm/vmx/vvmx.c |    8 ++++----
 1 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/xen/arch/x86/hvm/vmx/vvmx.c b/xen/arch/x86/hvm/vmx/vvmx.c
index e5d812a..9839642 100644
--- a/xen/arch/x86/hvm/vmx/vvmx.c
+++ b/xen/arch/x86/hvm/vmx/vvmx.c
@@ -530,8 +530,7 @@ static void nvmx_update_exit_control(struct vcpu *v, unsigned long host_cntrl)
     shadow_cntrl = __get_vvmcs(nvcpu->nv_vvmcx, VM_EXIT_CONTROLS);
     shadow_cntrl &= ~(VM_EXIT_SAVE_DEBUG_CNTRLS 
                       | VM_EXIT_SAVE_GUEST_PAT
-                      | VM_EXIT_SAVE_GUEST_EFER
-                      | VM_EXIT_SAVE_PREEMPT_TIMER);
+                      | VM_EXIT_SAVE_GUEST_EFER);
     shadow_cntrl |= host_cntrl;
     __vmwrite(VM_EXIT_CONTROLS, shadow_cntrl);
 }
@@ -1318,8 +1317,9 @@ int nvmx_msr_read_intercept(unsigned int msr, u64 *msr_content)
         /* 1-seetings */
         /* bit 0-8, 10,11,13,14,16,17 must be 1 (refer G4 of SDM) */
         tmp = 0x36dff;
-        data = VM_EXIT_ACK_INTR_ON_EXIT;
-        data |= VM_EXIT_IA32E_MODE;
+        data = VM_EXIT_ACK_INTR_ON_EXIT |
+               VM_EXIT_IA32E_MODE |
+               VM_EXIT_SAVE_PREEMPT_TIMER;
 	/* 0-settings */
         data = ((data | tmp) << 32) | tmp;
         break;
-- 
1.7.1

[PATCH 7/9] nested vmx: enable load and save IA32_PAT feature for L1 VMM

[Dongxiao Xu]

Signed-off-by: Dongxiao Xu <dongxiao.xu@intel.com>
---
 xen/arch/x86/hvm/vmx/vvmx.c |   22 ++++++++++++++++++----
 1 files changed, 18 insertions(+), 4 deletions(-)

diff --git a/xen/arch/x86/hvm/vmx/vvmx.c b/xen/arch/x86/hvm/vmx/vvmx.c
index 9839642..685fa59 100644
--- a/xen/arch/x86/hvm/vmx/vvmx.c
+++ b/xen/arch/x86/hvm/vmx/vvmx.c
@@ -529,7 +529,7 @@ static void nvmx_update_exit_control(struct vcpu *v, unsigned long host_cntrl)
 
     shadow_cntrl = __get_vvmcs(nvcpu->nv_vvmcx, VM_EXIT_CONTROLS);
     shadow_cntrl &= ~(VM_EXIT_SAVE_DEBUG_CNTRLS 
-                      | VM_EXIT_SAVE_GUEST_PAT
+                      | VM_EXIT_LOAD_HOST_PAT
                       | VM_EXIT_SAVE_GUEST_EFER);
     shadow_cntrl |= host_cntrl;
     __vmwrite(VM_EXIT_CONTROLS, shadow_cntrl);
@@ -624,6 +624,7 @@ static const u16 vmcs_gstate_field[] = {
     /* 64 BITS */
     VMCS_LINK_POINTER,
     GUEST_IA32_DEBUGCTL,
+    GUEST_PAT,
     /* 32 BITS */
     GUEST_ES_LIMIT,
     GUEST_CS_LIMIT,
@@ -746,6 +747,7 @@ static void load_shadow_guest_state(struct vcpu *v)
     struct nestedvcpu *nvcpu = &vcpu_nestedhvm(v);
     void *vvmcs = nvcpu->nv_vvmcx;
     int i;
+    u32 control;
 
     /* vvmcs.gstate to shadow vmcs.gstate */
     for ( i = 0; i < ARRAY_SIZE(vmcs_gstate_field); i++ )
@@ -755,6 +757,10 @@ static void load_shadow_guest_state(struct vcpu *v)
     hvm_set_cr4(__get_vvmcs(vvmcs, GUEST_CR4));
     hvm_set_cr3(__get_vvmcs(vvmcs, GUEST_CR3));
 
+    control = __get_vvmcs(vvmcs, VM_ENTRY_CONTROLS);
+    if ( control & VM_ENTRY_LOAD_GUEST_PAT )
+        hvm_set_guest_pat(v, __get_vvmcs(vvmcs, GUEST_PAT));
+
     hvm_funcs.set_tsc_offset(v, v->arch.hvm_vcpu.cache_tsc_offset);
 
     vvmcs_to_shadow(vvmcs, VM_ENTRY_INTR_INFO);
@@ -868,6 +874,7 @@ static void load_vvmcs_host_state(struct vcpu *v)
     int i;
     u64 r;
     void *vvmcs = vcpu_nestedhvm(v).nv_vvmcx;
+    u32 control;
 
     for ( i = 0; i < ARRAY_SIZE(vmcs_h2g_field); i++ )
     {
@@ -879,6 +886,10 @@ static void load_vvmcs_host_state(struct vcpu *v)
     hvm_set_cr4(__get_vvmcs(vvmcs, HOST_CR4));
     hvm_set_cr3(__get_vvmcs(vvmcs, HOST_CR3));
 
+    control = __get_vvmcs(vvmcs, VM_EXIT_CONTROLS);
+    if ( control & VM_EXIT_LOAD_HOST_PAT )
+        hvm_set_guest_pat(v, __get_vvmcs(vvmcs, HOST_PAT));
+
     hvm_funcs.set_tsc_offset(v, v->arch.hvm_vcpu.cache_tsc_offset);
 
     __set_vvmcs(vvmcs, VM_ENTRY_INTR_INFO, 0);
@@ -1319,14 +1330,17 @@ int nvmx_msr_read_intercept(unsigned int msr, u64 *msr_content)
         tmp = 0x36dff;
         data = VM_EXIT_ACK_INTR_ON_EXIT |
                VM_EXIT_IA32E_MODE |
-               VM_EXIT_SAVE_PREEMPT_TIMER;
+               VM_EXIT_SAVE_PREEMPT_TIMER |
+               VM_EXIT_SAVE_GUEST_PAT |
+               VM_EXIT_LOAD_HOST_PAT;
 	/* 0-settings */
         data = ((data | tmp) << 32) | tmp;
         break;
     case MSR_IA32_VMX_ENTRY_CTLS:
         /* bit 0-8, and 12 must be 1 (refer G5 of SDM) */
-        data = 0x11ff;
-        data = (data << 32) | data;
+        tmp = 0x11ff;
+        data = VM_ENTRY_LOAD_GUEST_PAT;
+        data = ((data | tmp) << 32) | tmp;
         break;
 
     case IA32_FEATURE_CONTROL_MSR:
-- 
1.7.1

[PATCH 8/9] nested vmx: enable load and save IA32_EFER feature for L1 VMM

[Dongxiao Xu]

Signed-off-by: Dongxiao Xu <dongxiao.xu@intel.com>
---
 xen/arch/x86/hvm/vmx/vvmx.c        |   10 +++++++---
 xen/include/asm-x86/hvm/vmx/vmcs.h |    4 ++++
 2 files changed, 11 insertions(+), 3 deletions(-)

diff --git a/xen/arch/x86/hvm/vmx/vvmx.c b/xen/arch/x86/hvm/vmx/vvmx.c
index 685fa59..fad961d 100644
--- a/xen/arch/x86/hvm/vmx/vvmx.c
+++ b/xen/arch/x86/hvm/vmx/vvmx.c
@@ -530,7 +530,7 @@ static void nvmx_update_exit_control(struct vcpu *v, unsigned long host_cntrl)
     shadow_cntrl = __get_vvmcs(nvcpu->nv_vvmcx, VM_EXIT_CONTROLS);
     shadow_cntrl &= ~(VM_EXIT_SAVE_DEBUG_CNTRLS 
                       | VM_EXIT_LOAD_HOST_PAT
-                      | VM_EXIT_SAVE_GUEST_EFER);
+                      | VM_EXIT_LOAD_HOST_EFER);
     shadow_cntrl |= host_cntrl;
     __vmwrite(VM_EXIT_CONTROLS, shadow_cntrl);
 }
@@ -625,6 +625,7 @@ static const u16 vmcs_gstate_field[] = {
     VMCS_LINK_POINTER,
     GUEST_IA32_DEBUGCTL,
     GUEST_PAT,
+    GUEST_EFER,
     /* 32 BITS */
     GUEST_ES_LIMIT,
     GUEST_CS_LIMIT,
@@ -1332,14 +1333,17 @@ int nvmx_msr_read_intercept(unsigned int msr, u64 *msr_content)
                VM_EXIT_IA32E_MODE |
                VM_EXIT_SAVE_PREEMPT_TIMER |
                VM_EXIT_SAVE_GUEST_PAT |
-               VM_EXIT_LOAD_HOST_PAT;
+               VM_EXIT_LOAD_HOST_PAT |
+               VM_EXIT_SAVE_GUEST_EFER |
+               VM_EXIT_LOAD_HOST_EFER;
 	/* 0-settings */
         data = ((data | tmp) << 32) | tmp;
         break;
     case MSR_IA32_VMX_ENTRY_CTLS:
         /* bit 0-8, and 12 must be 1 (refer G5 of SDM) */
         tmp = 0x11ff;
-        data = VM_ENTRY_LOAD_GUEST_PAT;
+        data = VM_ENTRY_LOAD_GUEST_PAT |
+               VM_ENTRY_LOAD_GUEST_EFER;
         data = ((data | tmp) << 32) | tmp;
         break;
 
diff --git a/xen/include/asm-x86/hvm/vmx/vmcs.h b/xen/include/asm-x86/hvm/vmx/vmcs.h
index fbe9a52..9665d3a 100644
--- a/xen/include/asm-x86/hvm/vmx/vmcs.h
+++ b/xen/include/asm-x86/hvm/vmx/vmcs.h
@@ -300,6 +300,8 @@ enum vmcs_field {
     GUEST_IA32_DEBUGCTL_HIGH        = 0x00002803,
     GUEST_PAT                       = 0x00002804,
     GUEST_PAT_HIGH                  = 0x00002805,
+    GUEST_EFER                      = 0x00002806,
+    GUEST_EFER_HIGH                 = 0x00002807,
     GUEST_PDPTR0                    = 0x0000280a,
     GUEST_PDPTR0_HIGH               = 0x0000280b,
     GUEST_PDPTR1                    = 0x0000280c,
@@ -310,6 +312,8 @@ enum vmcs_field {
     GUEST_PDPTR3_HIGH               = 0x00002811,
     HOST_PAT                        = 0x00002c00,
     HOST_PAT_HIGH                   = 0x00002c01,
+    HOST_EFER                       = 0x00002c02,
+    HOST_EFER_HIGH                  = 0x00002c03,
     PIN_BASED_VM_EXEC_CONTROL       = 0x00004000,
     CPU_BASED_VM_EXEC_CONTROL       = 0x00004002,
     EXCEPTION_BITMAP                = 0x00004004,
-- 
1.7.1

[PATCH 9/9] nested vmx: enable load IA32_PERF_GLOBAL_CTRL feature for L1 VMM

[Dongxiao Xu]

Signed-off-by: Dongxiao Xu <dongxiao.xu@intel.com>
---
 xen/arch/x86/hvm/vmx/vvmx.c        |   18 ++++++++++++++----
 xen/include/asm-x86/hvm/vmx/vmcs.h |    6 ++++++
 2 files changed, 20 insertions(+), 4 deletions(-)

diff --git a/xen/arch/x86/hvm/vmx/vvmx.c b/xen/arch/x86/hvm/vmx/vvmx.c
index fad961d..ed47780 100644
--- a/xen/arch/x86/hvm/vmx/vvmx.c
+++ b/xen/arch/x86/hvm/vmx/vvmx.c
@@ -530,7 +530,8 @@ static void nvmx_update_exit_control(struct vcpu *v, unsigned long host_cntrl)
     shadow_cntrl = __get_vvmcs(nvcpu->nv_vvmcx, VM_EXIT_CONTROLS);
     shadow_cntrl &= ~(VM_EXIT_SAVE_DEBUG_CNTRLS 
                       | VM_EXIT_LOAD_HOST_PAT
-                      | VM_EXIT_LOAD_HOST_EFER);
+                      | VM_EXIT_LOAD_HOST_EFER
+                      | VM_EXIT_LOAD_PERF_GLOBAL_CTRL);
     shadow_cntrl |= host_cntrl;
     __vmwrite(VM_EXIT_CONTROLS, shadow_cntrl);
 }
@@ -541,7 +542,9 @@ static void nvmx_update_entry_control(struct vcpu *v)
     struct nestedvcpu *nvcpu = &vcpu_nestedhvm(v);
 
     shadow_cntrl = __get_vvmcs(nvcpu->nv_vvmcx, VM_ENTRY_CONTROLS);
-    shadow_cntrl &= ~(VM_ENTRY_LOAD_GUEST_PAT | VM_ENTRY_LOAD_GUEST_EFER);
+    shadow_cntrl &= ~(VM_ENTRY_LOAD_GUEST_PAT
+                      | VM_ENTRY_LOAD_GUEST_EFER
+                      | VM_ENTRY_LOAD_PERF_GLOBAL_CTRL);
     __vmwrite(VM_ENTRY_CONTROLS, shadow_cntrl);
 }
 
@@ -626,6 +629,7 @@ static const u16 vmcs_gstate_field[] = {
     GUEST_IA32_DEBUGCTL,
     GUEST_PAT,
     GUEST_EFER,
+    GUEST_PERF_GLOBAL_CTRL,
     /* 32 BITS */
     GUEST_ES_LIMIT,
     GUEST_CS_LIMIT,
@@ -761,6 +765,8 @@ static void load_shadow_guest_state(struct vcpu *v)
     control = __get_vvmcs(vvmcs, VM_ENTRY_CONTROLS);
     if ( control & VM_ENTRY_LOAD_GUEST_PAT )
         hvm_set_guest_pat(v, __get_vvmcs(vvmcs, GUEST_PAT));
+    if ( control & VM_ENTRY_LOAD_PERF_GLOBAL_CTRL )
+        hvm_msr_write_intercept(MSR_CORE_PERF_GLOBAL_CTRL, __get_vvmcs(vvmcs, GUEST_PERF_GLOBAL_CTRL));
 
     hvm_funcs.set_tsc_offset(v, v->arch.hvm_vcpu.cache_tsc_offset);
 
@@ -890,6 +896,8 @@ static void load_vvmcs_host_state(struct vcpu *v)
     control = __get_vvmcs(vvmcs, VM_EXIT_CONTROLS);
     if ( control & VM_EXIT_LOAD_HOST_PAT )
         hvm_set_guest_pat(v, __get_vvmcs(vvmcs, HOST_PAT));
+    if ( control & VM_EXIT_LOAD_PERF_GLOBAL_CTRL )
+        hvm_msr_write_intercept(MSR_CORE_PERF_GLOBAL_CTRL, __get_vvmcs(vvmcs, HOST_PERF_GLOBAL_CTRL));
 
     hvm_funcs.set_tsc_offset(v, v->arch.hvm_vcpu.cache_tsc_offset);
 
@@ -1335,7 +1343,8 @@ int nvmx_msr_read_intercept(unsigned int msr, u64 *msr_content)
                VM_EXIT_SAVE_GUEST_PAT |
                VM_EXIT_LOAD_HOST_PAT |
                VM_EXIT_SAVE_GUEST_EFER |
-               VM_EXIT_LOAD_HOST_EFER;
+               VM_EXIT_LOAD_HOST_EFER |
+               VM_EXIT_LOAD_PERF_GLOBAL_CTRL;
 	/* 0-settings */
         data = ((data | tmp) << 32) | tmp;
         break;
@@ -1343,7 +1352,8 @@ int nvmx_msr_read_intercept(unsigned int msr, u64 *msr_content)
         /* bit 0-8, and 12 must be 1 (refer G5 of SDM) */
         tmp = 0x11ff;
         data = VM_ENTRY_LOAD_GUEST_PAT |
-               VM_ENTRY_LOAD_GUEST_EFER;
+               VM_ENTRY_LOAD_GUEST_EFER |
+               VM_ENTRY_LOAD_PERF_GLOBAL_CTRL;
         data = ((data | tmp) << 32) | tmp;
         break;
 
diff --git a/xen/include/asm-x86/hvm/vmx/vmcs.h b/xen/include/asm-x86/hvm/vmx/vmcs.h
index 9665d3a..cc92f69 100644
--- a/xen/include/asm-x86/hvm/vmx/vmcs.h
+++ b/xen/include/asm-x86/hvm/vmx/vmcs.h
@@ -162,6 +162,7 @@ extern u32 vmx_pin_based_exec_control;
 
 #define VM_EXIT_SAVE_DEBUG_CNTRLS       0x00000004
 #define VM_EXIT_IA32E_MODE              0x00000200
+#define VM_EXIT_LOAD_PERF_GLOBAL_CTRL   0x00001000
 #define VM_EXIT_ACK_INTR_ON_EXIT        0x00008000
 #define VM_EXIT_SAVE_GUEST_PAT          0x00040000
 #define VM_EXIT_LOAD_HOST_PAT           0x00080000
@@ -173,6 +174,7 @@ extern u32 vmx_vmexit_control;
 #define VM_ENTRY_IA32E_MODE             0x00000200
 #define VM_ENTRY_SMM                    0x00000400
 #define VM_ENTRY_DEACT_DUAL_MONITOR     0x00000800
+#define VM_ENTRY_LOAD_PERF_GLOBAL_CTRL  0x00002000
 #define VM_ENTRY_LOAD_GUEST_PAT         0x00004000
 #define VM_ENTRY_LOAD_GUEST_EFER        0x00008000
 extern u32 vmx_vmentry_control;
@@ -302,6 +304,8 @@ enum vmcs_field {
     GUEST_PAT_HIGH                  = 0x00002805,
     GUEST_EFER                      = 0x00002806,
     GUEST_EFER_HIGH                 = 0x00002807,
+    GUEST_PERF_GLOBAL_CTRL          = 0x00002808,
+    GUEST_PERF_GLOBAL_CTRL_HIGH     = 0x00002809,
     GUEST_PDPTR0                    = 0x0000280a,
     GUEST_PDPTR0_HIGH               = 0x0000280b,
     GUEST_PDPTR1                    = 0x0000280c,
@@ -314,6 +318,8 @@ enum vmcs_field {
     HOST_PAT_HIGH                   = 0x00002c01,
     HOST_EFER                       = 0x00002c02,
     HOST_EFER_HIGH                  = 0x00002c03,
+    HOST_PERF_GLOBAL_CTRL           = 0x00002c04,
+    HOST_PERF_GLOBAL_CTRL_HIGH      = 0x00002c05,
     PIN_BASED_VM_EXEC_CONTROL       = 0x00004000,
     CPU_BASED_VM_EXEC_CONTROL       = 0x00004002,
     EXCEPTION_BITMAP                = 0x00004004,
-- 
1.7.1

Re: [PATCH 0/9] nested vmx: expose some vmx features to L1 VMM

[Jan Beulich]

>>> On 28.11.12 at 08:11, Dongxiao Xu <dongxiao.xu@intel.com> wrote:
> This patch series expose some vmx features to L1 VMM, including MTF, 
> NMI-window exiting, etc.
> Please help to review and pull.

Looks reasonable to me, but clearly wants to be acked by at
least one of the formally listed VMX maintainers.

Jan

> Dongxiao Xu (9):
>   nested vmx: enable Monitor Trap Flag for L1 VMM
>   nested vmx: enable NMI-window exiting for L1 VMM
>   nested vmx: enable secondary processor-based VM-Execution controls
>   nested vmx: enable Descriptor-table exiting for L1 VMM
>   nested vmx: enable VMX-preemption timer for L1 VMM
>   nested vmx: enable save VMX-preemption timer feature for L1 VMM
>   nested vmx: enable load and save IA32_PAT feature for L1 VMM
>   nested vmx: enable load and save IA32_EFER feature for L1 VMM
>   nested vmx: enable load IA32_PERF_GLOBAL_CTRL feature for L1 VMM
> 
>  xen/arch/x86/hvm/vmx/vmx.c         |    2 +-
>  xen/arch/x86/hvm/vmx/vvmx.c        |  108 +++++++++++++++++++++++++++++++-----
>  xen/include/asm-x86/hvm/vmx/vmcs.h |   12 ++++
>  xen/include/asm-x86/hvm/vmx/vmx.h  |    1 +
>  4 files changed, 108 insertions(+), 15 deletions(-)
> 
> 
> _______________________________________________
> Xen-devel mailing list
> Xen-devel@lists.xen.org 
> http://lists.xen.org/xen-devel 

Re: [PATCH 0/9] nested vmx: expose some vmx features to L1 VMM

[Nakajima, Jun]

On Wed, Nov 28, 2012 at 2:08 AM, Jan Beulich <JBeulich@suse.com> wrote:
>
> >>> On 28.11.12 at 08:11, Dongxiao Xu <dongxiao.xu@intel.com> wrote:
> > This patch series expose some vmx features to L1 VMM, including MTF,
> > NMI-window exiting, etc.
> > Please help to review and pull.
>
> Looks reasonable to me, but clearly wants to be acked by at
> least one of the formally listed VMX maintainers.

Ack.

>
> Jan
>
> > Dongxiao Xu (9):
> >   nested vmx: enable Monitor Trap Flag for L1 VMM
> >   nested vmx: enable NMI-window exiting for L1 VMM
> >   nested vmx: enable secondary processor-based VM-Execution controls
> >   nested vmx: enable Descriptor-table exiting for L1 VMM
> >   nested vmx: enable VMX-preemption timer for L1 VMM
> >   nested vmx: enable save VMX-preemption timer feature for L1 VMM
> >   nested vmx: enable load and save IA32_PAT feature for L1 VMM
> >   nested vmx: enable load and save IA32_EFER feature for L1 VMM
> >   nested vmx: enable load IA32_PERF_GLOBAL_CTRL feature for L1 VMM
> >
> >  xen/arch/x86/hvm/vmx/vmx.c         |    2 +-
> >  xen/arch/x86/hvm/vmx/vvmx.c        |  108
> > +++++++++++++++++++++++++++++++-----
> >  xen/include/asm-x86/hvm/vmx/vmcs.h |   12 ++++
> >  xen/include/asm-x86/hvm/vmx/vmx.h  |    1 +
> >  4 files changed, 108 insertions(+), 15 deletions(-)
> >

--
Jun
Intel Open Source Technology Center