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From: Xiantao Zhang <xiantao.zhang@intel.com>
To: xen-devel@lists.xen.org
Cc: keir@xen.org, jun.nakajima@intel.com, tim@xen.org,
	eddie.dong@intel.com, JBeulich@suse.com,
	Zhang Xiantao <xiantao.zhang@intel.com>
Subject: [PATCH v2 08/10] nEPT: handle invept instruction from L1 VMM
Date: Thu, 20 Dec 2012 03:44:25 +0800	[thread overview]
Message-ID: <1355946267-24227-9-git-send-email-xiantao.zhang@intel.com> (raw)
In-Reply-To: <1355946267-24227-1-git-send-email-xiantao.zhang@intel.com>

From: Zhang Xiantao <xiantao.zhang@intel.com>

Add the INVEPT instruction emulation logic.

Signed-off-by: Zhang Xiantao <xiantao.zhang@intel.com>
---
 xen/arch/x86/hvm/vmx/vmx.c         |    6 +++-
 xen/arch/x86/hvm/vmx/vvmx.c        |   39 ++++++++++++++++++++++++++++++++++++
 xen/arch/x86/mm/p2m.c              |    2 +-
 xen/include/asm-x86/hvm/vmx/vvmx.h |    1 +
 4 files changed, 45 insertions(+), 3 deletions(-)

diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c
index e5be5a2..7af92cc 100644
--- a/xen/arch/x86/hvm/vmx/vmx.c
+++ b/xen/arch/x86/hvm/vmx/vmx.c
@@ -2572,11 +2572,13 @@ void vmx_vmexit_handler(struct cpu_user_regs *regs)
         if ( nvmx_handle_vmresume(regs) == X86EMUL_OKAY )
             update_guest_eip();
         break;
-
+    case EXIT_REASON_INVEPT:
+        if ( nvmx_handle_invept(regs) == X86EMUL_OKAY )
+            update_guest_eip();
+        break;
     case EXIT_REASON_MWAIT_INSTRUCTION:
     case EXIT_REASON_MONITOR_INSTRUCTION:
     case EXIT_REASON_GETSEC:
-    case EXIT_REASON_INVEPT:
     case EXIT_REASON_INVVPID:
         /*
          * We should never exit on GETSEC because CR4.SMXE is always 0 when
diff --git a/xen/arch/x86/hvm/vmx/vvmx.c b/xen/arch/x86/hvm/vmx/vvmx.c
index cb2c6e7..b7c3639 100644
--- a/xen/arch/x86/hvm/vmx/vvmx.c
+++ b/xen/arch/x86/hvm/vmx/vvmx.c
@@ -1356,6 +1356,45 @@ int nvmx_handle_vmwrite(struct cpu_user_regs *regs)
     return X86EMUL_OKAY;
 }
 
+int nvmx_handle_invept(struct cpu_user_regs *regs)
+{
+    struct vmx_inst_decoded decode;
+    unsigned long eptp;
+    u64 inv_type;
+
+    if ( !cpu_has_vmx_ept )
+        return X86EMUL_EXCEPTION;
+
+    if ( decode_vmx_inst(regs, &decode, &eptp, 0)
+             != X86EMUL_OKAY )
+        return X86EMUL_EXCEPTION;
+
+    inv_type = reg_read(regs, decode.reg2);
+    gdprintk(XENLOG_DEBUG,"inv_type:%ld, eptp:%lx\n", inv_type, eptp);
+
+    switch ( inv_type ) {
+    case INVEPT_SINGLE_CONTEXT:
+        {
+            struct p2m_domain *p2m = vcpu_nestedhvm(current).nv_p2m;
+            if ( p2m )
+            {
+	            p2m_flush(current, p2m);
+                ept_sync_domain(p2m);
+            }
+        }
+        break;
+    case INVEPT_ALL_CONTEXT:
+        p2m_flush_nestedp2m(current->domain);
+        __invept(INVEPT_ALL_CONTEXT, 0, 0);
+        break;
+    default:
+        return X86EMUL_EXCEPTION;
+    }
+    vmreturn(regs, VMSUCCEED);
+    return X86EMUL_OKAY;
+}
+
+
 #define __emul_value(enable1, default1) \
     ((enable1 | default1) << 32 | (default1))
 
diff --git a/xen/arch/x86/mm/p2m.c b/xen/arch/x86/mm/p2m.c
index 1f59410..17903ee 100644
--- a/xen/arch/x86/mm/p2m.c
+++ b/xen/arch/x86/mm/p2m.c
@@ -1465,7 +1465,7 @@ p2m_flush_table(struct p2m_domain *p2m)
 void
 p2m_flush(struct vcpu *v, struct p2m_domain *p2m)
 {
-    ASSERT(v->domain == p2m->domain);
+    ASSERT(p2m && v->domain == p2m->domain);
     vcpu_nestedhvm(v).nv_p2m = NULL;
     p2m_flush_table(p2m);
     hvm_asid_flush_vcpu(v);
diff --git a/xen/include/asm-x86/hvm/vmx/vvmx.h b/xen/include/asm-x86/hvm/vmx/vvmx.h
index 55c0ad1..cf5ed9a 100644
--- a/xen/include/asm-x86/hvm/vmx/vvmx.h
+++ b/xen/include/asm-x86/hvm/vmx/vvmx.h
@@ -190,6 +190,7 @@ int nvmx_handle_vmread(struct cpu_user_regs *regs);
 int nvmx_handle_vmwrite(struct cpu_user_regs *regs);
 int nvmx_handle_vmresume(struct cpu_user_regs *regs);
 int nvmx_handle_vmlaunch(struct cpu_user_regs *regs);
+int nvmx_handle_invept(struct cpu_user_regs *regs);
 int nvmx_msr_read_intercept(unsigned int msr,
                                 u64 *msr_content);
 int nvmx_msr_write_intercept(unsigned int msr,
-- 
1.7.1

  parent reply	other threads:[~2012-12-19 19:44 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2012-12-19 19:44 [PATCH v2 00/10] Nested VMX: Add virtual EPT & VPID support to L1 VMM Xiantao Zhang
2012-12-19 19:44 ` [PATCH v2 01/10] nestedhap: Change hostcr3 and p2m->cr3 to meaningful words Xiantao Zhang
2012-12-19  8:19   ` Jan Beulich
2012-12-19  8:40     ` Zhang, Xiantao
2012-12-19 19:44 ` [PATCH v2 02/10] nestedhap: Change nested p2m's walker to vendor-specific Xiantao Zhang
2012-12-19 19:44 ` [PATCH v2 03/10] nested_ept: Implement guest ept's walker Xiantao Zhang
2012-12-19 16:42   ` Nakajima, Jun
2012-12-19 19:44 ` [PATCH v2 04/10] EPT: Make ept data structure or operations neutral Xiantao Zhang
2012-12-19 19:44 ` [PATCH v2 05/10] nEPT: Try to enable EPT paging for L2 guest Xiantao Zhang
2012-12-19 17:16   ` Nakajima, Jun
2012-12-20  1:27     ` Zhang, Xiantao
2012-12-19 19:44 ` [PATCH v2 06/10] nEPT: Sync PDPTR fields if L2 guest in PAE paging mode Xiantao Zhang
2012-12-19 19:44 ` [PATCH v2 07/10] nEPT: Use minimal permission for nested p2m Xiantao Zhang
2012-12-19 19:44 ` Xiantao Zhang [this message]
2012-12-19  8:28   ` [PATCH v2 08/10] nEPT: handle invept instruction from L1 VMM Jan Beulich
2012-12-20  2:39     ` Zhang, Xiantao
2012-12-19 19:44 ` [PATCH v2 09/10] nVMX: virutalize VPID capability to nested VMM Xiantao Zhang
2012-12-19 19:44 ` [PATCH v2 10/10] nEPT: expost EPT & VPID capablities to L1 VMM Xiantao Zhang

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