From mboxrd@z Thu Jan 1 00:00:00 1970 From: Dongxiao Xu Subject: [PATCH v2 2/3] nested vmx: synchronize page fault error code match and mask Date: Mon, 7 Jan 2013 14:41:29 +0800 Message-ID: <1357540890-27886-3-git-send-email-dongxiao.xu@intel.com> References: <1357540890-27886-1-git-send-email-dongxiao.xu@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1357540890-27886-1-git-send-email-dongxiao.xu@intel.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: xen-devel@lists.xen.org List-Id: xen-devel@lists.xenproject.org Page fault is specially handled not only with exception bitmaps, but also with consideration of page fault error code mask/match values. Therefore in nested virtualization case, the two values need to be synchronized from virtual VMCS to shadow VMCS. Signed-off-by: Dongxiao Xu --- xen/arch/x86/hvm/vmx/vvmx.c | 12 ++++++++++++ 1 files changed, 12 insertions(+), 0 deletions(-) diff --git a/xen/arch/x86/hvm/vmx/vvmx.c b/xen/arch/x86/hvm/vmx/vvmx.c index 16fb3fd..0f13884 100644 --- a/xen/arch/x86/hvm/vmx/vvmx.c +++ b/xen/arch/x86/hvm/vmx/vvmx.c @@ -603,6 +603,17 @@ static void nvmx_update_tpr_threshold(struct vcpu *v) __vmwrite(TPR_THRESHOLD, 0); } +static void nvmx_update_pfec(struct vcpu *v) +{ + struct nestedvcpu *nvcpu = &vcpu_nestedhvm(v); + void *vvmcs = nvcpu->nv_vvmcx; + + __vmwrite(PAGE_FAULT_ERROR_CODE_MASK, + __get_vvmcs(vvmcs, PAGE_FAULT_ERROR_CODE_MASK)); + __vmwrite(PAGE_FAULT_ERROR_CODE_MATCH, + __get_vvmcs(vvmcs, PAGE_FAULT_ERROR_CODE_MATCH)); +} + static void __clear_current_vvmcs(struct vcpu *v) { struct nestedvcpu *nvcpu = &vcpu_nestedhvm(v); @@ -813,6 +824,7 @@ static void load_shadow_control(struct vcpu *v) nvmx_update_apic_access_address(v); nvmx_update_virtual_apic_address(v); nvmx_update_tpr_threshold(v); + nvmx_update_pfec(v); } static void load_shadow_guest_state(struct vcpu *v) -- 1.7.1