From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stefano Stabellini Subject: [PATCH v6 02/10] xen/arm: introduce flush_xen_data_tlb_range_va Date: Tue, 15 Jan 2013 19:05:48 +0000 Message-ID: <1358276756-6189-2-git-send-email-stefano.stabellini@eu.citrix.com> References: Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: xen-devel@lists.xensource.com Cc: tim@xen.org, Ian.Campbell@citrix.com, Stefano Stabellini List-Id: xen-devel@lists.xenproject.org Add flush_xen_data_tlb_range_va, that flushes a range of virtual addresses. Replace all the calls to flush_xen_data_tlb_va with calls to flush_xen_data_tlb_range_va and remove flush_xen_data_tlb_va. Changes in v5: - move the barriers outside the loop in flush_xen_data_tlb_range_va. Signed-off-by: Stefano Stabellini --- xen/arch/arm/mm.c | 8 ++++---- xen/include/asm-arm/page.h | 18 +++++++++++------- 2 files changed, 15 insertions(+), 11 deletions(-) diff --git a/xen/arch/arm/mm.c b/xen/arch/arm/mm.c index d97b3ea..56361eb 100644 --- a/xen/arch/arm/mm.c +++ b/xen/arch/arm/mm.c @@ -113,7 +113,7 @@ void set_fixmap(unsigned map, unsigned long mfn, unsigned attributes) pte.pt.ai = attributes; pte.pt.xn = 1; write_pte(xen_fixmap + third_table_offset(FIXMAP_ADDR(map)), pte); - flush_xen_data_tlb_va(FIXMAP_ADDR(map)); + flush_xen_data_tlb_range_va(FIXMAP_ADDR(map), PAGE_SIZE); } /* Remove a mapping from a fixmap entry */ @@ -121,7 +121,7 @@ void clear_fixmap(unsigned map) { lpae_t pte = {0}; write_pte(xen_fixmap + third_table_offset(FIXMAP_ADDR(map)), pte); - flush_xen_data_tlb_va(FIXMAP_ADDR(map)); + flush_xen_data_tlb_range_va(FIXMAP_ADDR(map), PAGE_SIZE); } /* Map a page of domheap memory */ @@ -185,7 +185,7 @@ void *map_domain_page(unsigned long mfn) * We may not have flushed this specific subpage at map time, * since we only flush the 4k page not the superpage */ - flush_xen_data_tlb_va(va); + flush_xen_data_tlb_range_va(va, PAGE_SIZE); return (void *)va; } @@ -245,7 +245,7 @@ void __init setup_pagetables(unsigned long boot_phys_offset, paddr_t xen_paddr) dest_va = BOOT_MISC_VIRT_START; pte = mfn_to_xen_entry(xen_paddr >> PAGE_SHIFT); write_pte(xen_second + second_table_offset(dest_va), pte); - flush_xen_data_tlb_va(dest_va); + flush_xen_data_tlb_range_va(dest_va, PAGE_SIZE); /* Calculate virt-to-phys offset for the new location */ phys_offset = xen_paddr - (unsigned long) _start; diff --git a/xen/include/asm-arm/page.h b/xen/include/asm-arm/page.h index 5779cf4..090d93f 100644 --- a/xen/include/asm-arm/page.h +++ b/xen/include/asm-arm/page.h @@ -316,16 +316,20 @@ static inline void flush_xen_data_tlb(void) } /* - * Flush one VA's hypervisor mappings from the data TLB. This is not + * Flush a range of VA's hypervisor mappings from the data TLB. This is not * sufficient when changing code mappings or for self modifying code. */ -static inline void flush_xen_data_tlb_va(unsigned long va) +static inline void flush_xen_data_tlb_range_va(unsigned long va, unsigned long size) { - asm volatile("dsb;" /* Ensure preceding are visible */ - STORE_CP32(0, TLBIMVAH) - "dsb;" /* Ensure completion of the TLB flush */ - "isb;" - : : "r" (va) : "memory"); + unsigned long end = va + size; + dsb(); /* Ensure preceding are visible */ + while ( va < end ) { + asm volatile(STORE_CP32(0, TLBIMVAH) + : : "r" (va) : "memory"); + va += PAGE_SIZE; + } + dsb(); /* Ensure completion of the TLB flush */ + isb(); } /* Flush all non-hypervisor mappings from the TLB */ -- 1.7.2.5