From: Boris Ostrovsky <boris.ostrovsky@oracle.com>
To: dietmar.hahn@ts.fujitsu.com, suravee.suthikulpanit@amd.com,
jun.nakajima@intel.com, haitao.shan@intel.com,
jacob.shin@amd.com
Cc: Boris Ostrovsky <boris.ostrovsky@oracle.com>, xen-devel@lists.xen.org
Subject: [PATCH 0/8] Various VPMU patches
Date: Tue, 9 Apr 2013 13:26:11 -0400 [thread overview]
Message-ID: <1365528379-2516-1-git-send-email-boris.ostrovsky@oracle.com> (raw)
Here is a set of VPMU changes that I thought might be useful.
The first two patches are to avoid VMEXITs on certain MSR accesses. This
is already part of VMX so I added similar SVM code
The third patch should address the problem that Suravee mentioned on the
list a few weeks ago (http://lists.xen.org/archives/html/xen-devel/2013-03/msg00087.html).
It's a slightly different solution then what he suggested.
4th patch stops counters on AMD when VCPU is de-scheduled
5th is trivial Haswell support (new model number)
6th patch is trying to factor out common code from VMX and SVM.
7th is lazy VPMU save/restore. It is optimized for the case when CPUs are
not over-subscribed and VCPU stays on the same processor most of the time.
It is more beneficial on Intel processors because HW will keep track of
guest/host global control register in VMCS and tehrefore we don't need to
explicitly stop the counters. On AMD we do need to do this and so while
there is improvement, it is not as pronounced.
Here are some numbers that I managed to collect while running guests with
oprofile. This is number of executed instructions in vpmu_save/vpmu_load.
Eager VPMU Lazy VPMU
Save Restore Save Restore
Intel 181 225 46 50
AMD 132 104 80 102
When processors are oversubscribed, lazy restore may take about 2.5 times
as many instructions as in the dedicated case if new VCPU jumps onto the
processor (which doesn't happen on every context switch).
-boris
Boris Ostrovsky (8):
x86/AMD: Allow more fine-grained control of VMCB MSR Permission Map
x86/AMD: Do not intercept access to performance counters MSRs
x86/AMD: Read VPMU MSRs from context when it is not loaded into HW
x86/AMD: Stop counters on VPMU save
x86/VPMU: Add Haswell support
x86/VPMU: Factor out VPMU common code
x86/VPMU: Save/restore VPMU only when necessary
x86/AMD: Clean up context_update() in AMD VPMU code
xen/arch/x86/domain.c | 14 ++-
xen/arch/x86/hvm/svm/svm.c | 19 ++--
xen/arch/x86/hvm/svm/vpmu.c | 188 +++++++++++++++++++++++--------
xen/arch/x86/hvm/vmx/vmx.c | 2 -
xen/arch/x86/hvm/vmx/vpmu_core2.c | 48 ++++----
xen/arch/x86/hvm/vpmu.c | 114 +++++++++++++++++--
xen/include/asm-x86/hvm/svm/vmcb.h | 8 +-
xen/include/asm-x86/hvm/vmx/vpmu_core2.h | 1 -
xen/include/asm-x86/hvm/vpmu.h | 6 +-
9 files changed, 296 insertions(+), 104 deletions(-)
--
1.8.1.2
next reply other threads:[~2013-04-09 17:26 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-04-09 17:26 Boris Ostrovsky [this message]
2013-04-09 17:26 ` [PATCH 1/8] x86/AMD: Allow more fine-grained control of VMCB MSR Permission Map Boris Ostrovsky
2013-04-09 17:26 ` [PATCH 2/8] x86/AMD: Do not intercept access to performance counters MSRs Boris Ostrovsky
2013-04-10 13:25 ` Jan Beulich
2013-04-09 17:26 ` [PATCH 3/8] x86/AMD: Read VPMU MSRs from context when it is not loaded into HW Boris Ostrovsky
2013-04-11 18:26 ` Suravee Suthikulpanit
2013-04-11 18:34 ` Boris Ostrovsky
2013-04-11 19:30 ` Suravee Suthikulpanit
2013-04-16 15:41 ` Konrad Rzeszutek Wilk
2013-04-16 17:12 ` Jacob Shin
2013-04-16 18:36 ` Konrad Rzeszutek Wilk
2013-06-19 22:56 ` Suravee Suthikulanit
2013-06-19 23:32 ` Boris Ostrovsky
2013-06-19 23:53 ` Boris Ostrovsky
2013-04-09 17:26 ` [PATCH 4/8] x86/AMD: Stop counters on VPMU save Boris Ostrovsky
2013-04-09 17:26 ` [PATCH 5/8] x86/VPMU: Add Haswell support Boris Ostrovsky
2013-04-09 17:26 ` [PATCH 6/8] x86/VPMU: Factor out VPMU common code Boris Ostrovsky
2013-04-10 16:03 ` Nakajima, Jun
2013-04-09 17:26 ` [PATCH 7/8] x86/VPMU: Save/restore VPMU only when necessary Boris Ostrovsky
2013-04-10 8:57 ` Dietmar Hahn
2013-04-10 12:53 ` Boris Ostrovsky
2013-04-09 17:26 ` [PATCH 8/8] x86/AMD: Clean up context_update() in AMD VPMU code Boris Ostrovsky
2013-04-11 19:48 ` Suravee Suthikulpanit
2013-04-11 20:42 ` Boris Ostrovsky
2013-04-10 8:57 ` [PATCH 0/8] Various VPMU patches Dietmar Hahn
2013-04-10 18:49 ` Suravee Suthikulanit
2013-04-10 19:10 ` Boris Ostrovsky
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1365528379-2516-1-git-send-email-boris.ostrovsky@oracle.com \
--to=boris.ostrovsky@oracle.com \
--cc=dietmar.hahn@ts.fujitsu.com \
--cc=haitao.shan@intel.com \
--cc=jacob.shin@amd.com \
--cc=jun.nakajima@intel.com \
--cc=suravee.suthikulpanit@amd.com \
--cc=xen-devel@lists.xen.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).