From mboxrd@z Thu Jan 1 00:00:00 1970 From: Bamvor Jian Zhang Subject: [PATCH 4/4] xen/arm: enable switch to hyper mode for sun6i Date: Fri, 31 May 2013 20:53:34 +0800 Message-ID: <1370004814-30686-5-git-send-email-bjzhang@suse.com> References: <1370004814-30686-1-git-send-email-bjzhang@suse.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1370004814-30686-1-git-send-email-bjzhang@suse.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: xen-devel@lists.xen.org Cc: bjzhang@suse.com, andre.przywara@calxeda.com, julien.grall@linaro.org, ian.campbell@citrix.com, Stefano.Stabellini@eu.citrix.com List-Id: xen-devel@lists.xenproject.org Signed-off-by: Bamvor Jian Zhang --- xen/arch/arm/arm32/mode_switch.S | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/xen/arch/arm/arm32/mode_switch.S b/xen/arch/arm/arm32/mode_switch.S index c92a1cf..0fc26e0 100644 --- a/xen/arch/arm/arm32/mode_switch.S +++ b/xen/arch/arm/arm32/mode_switch.S @@ -21,6 +21,7 @@ #include #include #include +#include #include #include @@ -90,15 +91,23 @@ enter_hyp_mode: bic r0, r0, #0xe /* Clear EA, FIQ and IRQ */ mcr CP32(r0, SCR) - ldr r2, =MACH_TYPE_SMDK5250 /* r4 := Arndale machine ID */ /* By default load Arndale defaults values */ + ldr r2, =MACH_TYPE_SMDK5250 /* r4 := Arndale machine ID */ ldr r0, =EXYNOS5_TIMER_FREQUENCY /* r0 := timer's frequency */ ldr r1, =EXYNOS5_GIC_BASE_ADDRESS /* r1 := GIC base address */ - /* If it's not the Arndale machine ID, load VE values */ teq r5, r2 + beq board_set_done + /* If it's not the Arndale machine ID, try sun6i */ + ldr r2, =MACH_TYPE_SUN6I /* r2 := sun6i machine ID */ + ldr r0, =SUN6I_TIMER_FREQUENCY /* r0 := timer's frequency */ + ldr r1, =SUN6I_GIC_BASE_ADDRESS /* r1 := GIC base address */ + teq r5, r2 + beq board_set_done + /* If it's not the sun6i machine ID, load VE values */ ldrne r0, =V2M_TIMER_FREQUENCY ldrne r1, =V2M_GIC_BASE_ADDRESS +board_set_done: /* Ugly: the system timer's frequency register is only * programmable in Secure state. Since we don't know where its * memory-mapped control registers live, we can't find out the -- 1.8.1.4