[PATCH] xen: arm: remove unnecessary cache flush in write_pte

[Ian Campbell <ian.campbell@citrix.com>]

On a ARMv7/v8 SMP system the MMU is coherent

Suggested-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
---
 xen/include/asm-arm/arm32/page.h |    2 --
 xen/include/asm-arm/arm64/page.h |    2 --
 2 files changed, 0 insertions(+), 4 deletions(-)

diff --git a/xen/include/asm-arm/arm32/page.h b/xen/include/asm-arm/arm32/page.h
index 38bcffd..3a06a22 100644
--- a/xen/include/asm-arm/arm32/page.h
+++ b/xen/include/asm-arm/arm32/page.h
@@ -16,8 +16,6 @@ static inline void write_pte(lpae_t *p, lpae_t pte)
         /* Safely write the entry (STRD is atomic on CPUs that support LPAE) */
         "strd %0, %H0, [%1];"
         "dsb;"
-        /* Push this cacheline to the PoC so the rest of the system sees it. */
-        STORE_CP32(1, DCCMVAC)
         /* Ensure that the data flush is completed before proceeding */
         "dsb;"
         : : "r" (pte.bits), "r" (p) : "memory");
diff --git a/xen/include/asm-arm/arm64/page.h b/xen/include/asm-arm/arm64/page.h
index bd48fe3..542f886 100644
--- a/xen/include/asm-arm/arm64/page.h
+++ b/xen/include/asm-arm/arm64/page.h
@@ -11,8 +11,6 @@ static inline void write_pte(lpae_t *p, lpae_t pte)
         "dsb sy;"
         "str %0, [%1];"         /* Write the entry */
         "dsb sy;"
-        /* Push this cacheline to the PoC so the rest of the system sees it. */
-        "dc cvac, %1;"
         /* Ensure that the data flush is completed before proceeding */
         "dsb sy;"
         : : "r" (pte.bits), "r" (p) : "memory");
-- 
1.7.2.5