[PATCH 10/17] xen: arm: some cleanups to hypervisor entry code.

[Ian Campbell <ian.campbell@citrix.com>]

Tweak the case of some system registers for consistency.

There is no need to export return_to_hypervisor or return_to_guest.

Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
---
v4: split out from "xen: arm: handle traps from 64-bit guests"
    Do not export return_to_guest either.
---
 xen/arch/arm/arm32/entry.S |    4 ++--
 xen/arch/arm/arm64/entry.S |   16 ++++++++--------
 2 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/xen/arch/arm/arm32/entry.S b/xen/arch/arm/arm32/entry.S
index 1c26835..6cdf0aa 100644
--- a/xen/arch/arm/arm32/entry.S
+++ b/xen/arch/arm/arm32/entry.S
@@ -93,7 +93,7 @@ ENTRY(return_to_new_vcpu)
         cmp r11, #PSR_MODE_HYP
         beq return_to_hypervisor
         /* Fall thru */
-ENTRY(return_to_guest)
+return_to_guest:
         mov r11, sp
         bic sp, #7 /* Align the stack pointer */
         bl leave_hypervisor_tail /* Disables interrupts on return */
@@ -108,7 +108,7 @@ ENTRY(return_to_guest)
         RESTORE_ONE_BANKED(R8_fiq); RESTORE_ONE_BANKED(R9_fiq); RESTORE_ONE_BANKED(R10_fiq)
         RESTORE_ONE_BANKED(R11_fiq); RESTORE_ONE_BANKED(R12_fiq);
         /* Fall thru */
-ENTRY(return_to_hypervisor)
+return_to_hypervisor:
         cpsid i
         ldr lr, [sp, #UREGS_lr]
         ldr r11, [sp, #UREGS_pc]
diff --git a/xen/arch/arm/arm64/entry.S b/xen/arch/arm/arm64/entry.S
index b5af1e2..c0d2bd8 100644
--- a/xen/arch/arm/arm64/entry.S
+++ b/xen/arch/arm/arm64/entry.S
@@ -26,7 +26,7 @@ lr      .req    x30             // link register
         .macro  entry_guest, compat
 
         add     x21, sp, #UREGS_SPSR_el1
-        mrs     x23, SPSR_EL1
+        mrs     x23, SPSR_el1
         str     x23, [x21]
 
         .if \compat == 0 /* Aarch64 mode */
@@ -40,16 +40,16 @@ lr      .req    x30             // link register
         mrs     x23, ELR_el1
         stp     x22, x23, [x21]
 
-        .else             /* Aarch32 mode */
+        .else            /* Aarch32 mode */
 
         add     x21, sp, #UREGS_SPSR_fiq
-        mrs     x22, spsr_fiq
-        mrs     x23, spsr_irq
+        mrs     x22, SPSR_fiq
+        mrs     x23, SPSR_irq
         stp     w22, w23, [x21]
 
         add     x21, sp, #UREGS_SPSR_und
-        mrs     x22, spsr_und
-        mrs     x23, spsr_abt
+        mrs     x22, SPSR_und
+        mrs     x23, SPSR_abt
         stp     w22, w23, [x21]
 
         .endif
@@ -186,10 +186,10 @@ ENTRY(return_to_new_vcpu)
         ccmp    x21, #PSR_MODE_EL2h, #0x4, ne
         b.eq    return_to_hypervisor /* Yes */
         /* Fall thru */
-ENTRY(return_to_guest)
+return_to_guest:
         bl      leave_hypervisor_tail /* Disables interrupts on return */
         /* Fall thru */
-ENTRY(return_to_hypervisor)
+return_to_hypervisor:
         msr     daifset, #2 /* Mask interrupts */
 
         ldp     x21, x22, [sp, #UREGS_PC]       // load ELR, SPSR
-- 
1.7.2.5