From mboxrd@z Thu Jan 1 00:00:00 1970 From: Yang Zhang Subject: [PATCH 7/7] Nested VMX: Clear APIC-v control bit in vmcs02 Date: Fri, 9 Aug 2013 16:49:35 +0800 Message-ID: <1376038175-18571-8-git-send-email-yang.z.zhang@intel.com> References: <1376038175-18571-1-git-send-email-yang.z.zhang@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1376038175-18571-1-git-send-email-yang.z.zhang@intel.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: xen-devel@lists.xensource.com Cc: Yang Zhang , keir.xen@gmail.com, JBeulich@suse.com List-Id: xen-devel@lists.xenproject.org From: Yang Zhang There is no vAPIC-v supporting, so mask APIC-v control bit when constructing vmcs02. Signed-off-by: Yang Zhang --- xen/arch/x86/hvm/vmx/vvmx.c | 3 +++ 1 files changed, 3 insertions(+), 0 deletions(-) diff --git a/xen/arch/x86/hvm/vmx/vvmx.c b/xen/arch/x86/hvm/vmx/vvmx.c index 9ba169d..eed09be 100644 --- a/xen/arch/x86/hvm/vmx/vvmx.c +++ b/xen/arch/x86/hvm/vmx/vvmx.c @@ -617,6 +617,8 @@ void nvmx_update_secondary_exec_control(struct vcpu *v, shadow_cntrl = __get_vvmcs(nvcpu->nv_vvmcx, SECONDARY_VM_EXEC_CONTROL); nvmx->ept.enabled = !!(shadow_cntrl & SECONDARY_EXEC_ENABLE_EPT); shadow_cntrl |= host_cntrl; + shadow_cntrl &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT | + SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); __vmwrite(SECONDARY_VM_EXEC_CONTROL, shadow_cntrl); } @@ -627,6 +629,7 @@ static void nvmx_update_pin_control(struct vcpu *v, unsigned long host_cntrl) shadow_cntrl = __get_vvmcs(nvcpu->nv_vvmcx, PIN_BASED_VM_EXEC_CONTROL); shadow_cntrl |= host_cntrl; + shadow_cntrl &= ~PIN_BASED_POSTED_INTERRUPT; __vmwrite(PIN_BASED_VM_EXEC_CONTROL, shadow_cntrl); } -- 1.7.1