From mboxrd@z Thu Jan 1 00:00:00 1970 From: Yang Zhang Subject: [PATCH v3 2/4] Nested VMX: Force check ISR when L2 is running Date: Thu, 22 Aug 2013 15:24:58 +0800 Message-ID: <1377156300-32215-3-git-send-email-yang.z.zhang@intel.com> References: <1377156300-32215-1-git-send-email-yang.z.zhang@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1377156300-32215-1-git-send-email-yang.z.zhang@intel.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: xen-devel@lists.xensource.com Cc: Yang Zhang , Andrew.Cooper3@citrix.com, eddie.dong@intel.com, jun.nakajima@intel.com, JBeulich@suse.com List-Id: xen-devel@lists.xenproject.org From: Yang Zhang External interrupt is allowed to notify CPU only when it has higher priority than current in servicing interrupt. With APIC-v, the priority comparing is done by hardware and hardware will inject the interrupt to VCPU when it recognizes an interrupt. Currently, there is no virtual APIC-v feature available for L1 to use, so when L2 is running, we still need to compare interrupt priority with ISR in hypervisor instead via hardware. Signed-off-by: Yang Zhang --- xen/arch/x86/hvm/vlapic.c | 4 +++- 1 files changed, 3 insertions(+), 1 deletions(-) diff --git a/xen/arch/x86/hvm/vlapic.c b/xen/arch/x86/hvm/vlapic.c index 7a154f9..f1530fd 100644 --- a/xen/arch/x86/hvm/vlapic.c +++ b/xen/arch/x86/hvm/vlapic.c @@ -37,6 +37,7 @@ #include #include #include +#include #include #include @@ -1037,7 +1038,8 @@ int vlapic_has_pending_irq(struct vcpu *v) if ( irr == -1 ) return -1; - if ( vlapic_virtual_intr_delivery_enabled() ) + if ( vlapic_virtual_intr_delivery_enabled() && + !nestedhvm_vcpu_in_guestmode(v) ) return irr; isr = vlapic_find_highest_isr(vlapic); -- 1.7.1