From mboxrd@z Thu Jan 1 00:00:00 1970 From: Yang Zhang Subject: [PATCH v3 3/4] Nested VMX: Clear APIC-v control bit in vmcs02 Date: Thu, 22 Aug 2013 15:24:59 +0800 Message-ID: <1377156300-32215-4-git-send-email-yang.z.zhang@intel.com> References: <1377156300-32215-1-git-send-email-yang.z.zhang@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1377156300-32215-1-git-send-email-yang.z.zhang@intel.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: xen-devel@lists.xensource.com Cc: Yang Zhang , Andrew.Cooper3@citrix.com, eddie.dong@intel.com, jun.nakajima@intel.com, JBeulich@suse.com List-Id: xen-devel@lists.xenproject.org From: Yang Zhang There is no vAPIC-v supporting, so mask APIC-v control bit when constructing vmcs02. Signed-off-by: Yang Zhang --- xen/arch/x86/hvm/vmx/vvmx.c | 12 ++++++++++++ 1 files changed, 12 insertions(+), 0 deletions(-) diff --git a/xen/arch/x86/hvm/vmx/vvmx.c b/xen/arch/x86/hvm/vmx/vvmx.c index 5dfbc54..4792019 100644 --- a/xen/arch/x86/hvm/vmx/vvmx.c +++ b/xen/arch/x86/hvm/vmx/vvmx.c @@ -613,8 +613,15 @@ void nvmx_update_secondary_exec_control(struct vcpu *v, u32 shadow_cntrl; struct nestedvcpu *nvcpu = &vcpu_nestedhvm(v); struct nestedvmx *nvmx = &vcpu_2_nvmx(v); + u32 apicv_bit = SECONDARY_EXEC_APIC_REGISTER_VIRT | + SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY; + host_cntrl &= ~apicv_bit; shadow_cntrl = __get_vvmcs(nvcpu->nv_vvmcx, SECONDARY_VM_EXEC_CONTROL); + + /* No vAPIC-v support, so it shouldn't be set in vmcs12. */ + ASSERT( !(shadow_cntrl & apicv_bit) ); + nvmx->ept.enabled = !!(shadow_cntrl & SECONDARY_EXEC_ENABLE_EPT); shadow_cntrl |= host_cntrl; __vmwrite(SECONDARY_VM_EXEC_CONTROL, shadow_cntrl); @@ -625,7 +632,12 @@ static void nvmx_update_pin_control(struct vcpu *v, unsigned long host_cntrl) u32 shadow_cntrl; struct nestedvcpu *nvcpu = &vcpu_nestedhvm(v); + host_cntrl &= ~PIN_BASED_POSTED_INTERRUPT; shadow_cntrl = __get_vvmcs(nvcpu->nv_vvmcx, PIN_BASED_VM_EXEC_CONTROL); + + /* No vAPIC-v support, so it shouldn't be set in vmcs12. */ + ASSERT( !(shadow_cntrl & PIN_BASED_POSTED_INTERRUPT) ); + shadow_cntrl |= host_cntrl; __vmwrite(PIN_BASED_VM_EXEC_CONTROL, shadow_cntrl); } -- 1.7.1