From mboxrd@z Thu Jan 1 00:00:00 1970 From: Matt Wilson Subject: [PATCH 1/2] x86: remove X86_INTEL_USERCOPY code Date: Fri, 30 Aug 2013 02:14:08 +0000 Message-ID: <1377828849-18059-1-git-send-email-msw@amazon.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail6.bemta3.messagelabs.com ([195.245.230.39]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1VFEF9-0003Ow-GB for xen-devel@lists.xenproject.org; Fri, 30 Aug 2013 02:15:23 +0000 Received: from ex10-hub-31006.ant.amazon.com (ex10-hub-31006.sea31.amazon.com [10.185.176.13]) by smtp-in-31001.sea31.amazon.com (8.13.8/8.13.8) with ESMTP id r7U2FHtt023016 (version=TLSv1/SSLv3 cipher=AES128-SHA bits=128 verify=OK) for ; Fri, 30 Aug 2013 02:15:18 GMT List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: xen-devel@lists.xenproject.org List-Id: xen-devel@lists.xenproject.org Nothing defines CONFIG_X86_INTEL_USERCOPY, and as far as I can tell it was never used even when Xen supported 32-bit x86. Signed-off-by: Matt Wilson --- xen/arch/x86/cpu/intel.c | 21 --------------------- 1 files changed, 0 insertions(+), 21 deletions(-) diff --git a/xen/arch/x86/cpu/intel.c b/xen/arch/x86/cpu/intel.c index 9b71d36..072ecbc 100644 --- a/xen/arch/x86/cpu/intel.c +++ b/xen/arch/x86/cpu/intel.c @@ -18,13 +18,6 @@ #define select_idle_routine(x) ((void)0) -#ifdef CONFIG_X86_INTEL_USERCOPY -/* - * Alignment at which movsl is preferred for bulk memory copies. - */ -struct movsl_mask movsl_mask __read_mostly; -#endif - static unsigned int probe_intel_cpuid_faulting(void) { uint64_t x; @@ -229,20 +222,6 @@ static void __devinit init_intel(struct cpuinfo_x86 *c) /* Work around errata */ Intel_errata_workarounds(c); -#ifdef CONFIG_X86_INTEL_USERCOPY - /* - * Set up the preferred alignment for movsl bulk memory moves - */ - switch (c->x86) { - case 6: /* PII/PIII only like movsl with 8-byte alignment */ - movsl_mask.mask = 7; - break; - case 15: /* P4 is OK down to 8-byte alignment */ - movsl_mask.mask = 7; - break; - } -#endif - if ((c->x86 == 0xf && c->x86_model >= 0x03) || (c->x86 == 0x6 && c->x86_model >= 0x0e)) set_bit(X86_FEATURE_CONSTANT_TSC, c->x86_capability); -- 1.7.4.5