From mboxrd@z Thu Jan  1 00:00:00 1970
From: Dario Faggioli <dario.faggioli@citrix.com>
Subject: Re: [PATCH 0/5] xl: allow for node-wise specification
 of vcpu pinning
Date: Mon, 16 Sep 2013 20:47:49 +0200
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On lun, 2013-09-16 at 20:40 +0200, Dario Faggioli wrote:
> Hi all,
>=20
> Take 3 of this series. It allows for specifying vcpu pinning taking NUMA =
nodes
> into account. IOW, something like this:
>=20
>  * "nodes:0-3": all pCPUs of nodes 0,1,2,3;
>  * "nodes:0-3,^node:2": all pCPUS of nodes 0,1,3;
>  * "1,nodes:1-2,^6": pCPU 1 plus all pCPUs of nodes 1,2
>    but not pCPU 6;
>=20
> All comments that v2 got have been addressed. In particular, the test scr=
ipt
> has been rearranged and enhanced to match the requested behavior (generat=
e a
> test vector file and then read it).
>=20
And of course I forgot to put a "v3" tag in the subject line.

Also, here's the git tree for this version of the series:

 git://xenbits.xen.org/people/dariof/xen.git numa/xl-vcpupin-nodewise-v3
 http://xenbits.xen.org/gitweb/?p=3Dpeople/dariof/xen.git;a=3Dshortlog;h=3D=
refs/heads/numa/xl-vcpupin-nodewise-v3

Sorry,
Dario

--=20
<<This happens because I choose it to happen!>> (Raistlin Majere)
-----------------------------------------------------------------
Dario Faggioli, Ph.D, http://about.me/dario.faggioli
Senior Software Engineer, Citrix Systems R&D Ltd., Cambridge (UK)


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