From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ian Campbell Subject: [PATCH v2 8/9] xen: arm: configure TCR_EL2 for 40 bit physical address space Date: Thu, 26 Sep 2013 11:49:15 +0100 Message-ID: <1380192556-30700-8-git-send-email-ian.campbell@citrix.com> References: <1380192538.29483.63.camel@kazak.uk.xensource.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1380192538.29483.63.camel@kazak.uk.xensource.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: xen-devel@lists.xen.org Cc: julien.grall@linaro.org, tim@xen.org, Ian Campbell , stefano.stabellini@eu.citrix.com List-Id: xen-devel@lists.xenproject.org Signed-off-by: Ian Campbell Acked-by: Julien Grall Acked-by: Tim Deegan --- xen/arch/arm/arm64/head.S | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/xen/arch/arm/arm64/head.S b/xen/arch/arm/arm64/head.S index 0525720..1d04efc 100644 --- a/xen/arch/arm/arm64/head.S +++ b/xen/arch/arm/arm64/head.S @@ -215,12 +215,12 @@ skip_bss: msr mair_el2, x0 /* Set up the HTCR: - * PASize -- 4G + * PASize -- 40 bits / 1TB * Top byte is used * PT walks use Outer-Shareable accesses, * PT walks are write-back, write-allocate in both cache levels, * Full 64-bit address space goes through this table. */ - ldr x0, =0x80802500 + ldr x0, =0x80822500 msr tcr_el2, x0 /* Set up the SCTLR_EL2: -- 1.7.10.4