From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ian Campbell Subject: [PATCH 2/5] xen: arm: Enable 40 bit addressing in VTCR for arm64 Date: Mon, 7 Oct 2013 12:38:13 +0100 Message-ID: <1381145896-25890-2-git-send-email-ian.campbell@citrix.com> References: <1381145870.21562.93.camel@kazak.uk.xensource.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1381145870.21562.93.camel@kazak.uk.xensource.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: xen-devel@lists.xen.org Cc: julien.grall@linaro.org, tim@xen.org, Ian Campbell , anup.patel@linaro.org, stefano.stabellini@eu.citrix.com List-Id: xen-devel@lists.xenproject.org This requires setting the v8 specific VTCR_EL2.PS field. These bits are UNK/SBZP on v7. Also the TS0SZ field is described slightly differently for v8, so update the comment to reflect this. Signed-off-by: Ian Campbell --- xen/arch/arm/mm.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/xen/arch/arm/mm.c b/xen/arch/arm/mm.c index 0b53200..e48d473 100644 --- a/xen/arch/arm/mm.c +++ b/xen/arch/arm/mm.c @@ -386,9 +386,16 @@ void __cpuinit setup_virt_paging(void) /* Setup Stage 2 address translation */ /* SH0=00, ORGN0=IRGN0=01 * SL0=01 (Level-1) - * T0SZ=(1)1000 = -8 (40 bit physical addresses) + * ARVv7: T0SZ=(1)1000 = -8 (32-(-8) = 40 bit physical addresses) + * ARMv8: T0SZ=01 1000 = 24 (64-24 = 40 bit physical addresses) + * PS=010 == 40 bits */ - WRITE_SYSREG32(0x80002558, VTCR_EL2); isb(); +#ifdef CONFIG_ARM_32 + WRITE_SYSREG32(0x80002558, VTCR_EL2); +#else + WRITE_SYSREG32(0x80022558, VTCR_EL2); +#endif + isb(); } static inline lpae_t pte_of_xenaddr(vaddr_t va) -- 1.7.10.4